Yin Fengwei 13a50c929d hv: Explicitly trap VMXE and PCIDE bit for CR4 write ... Now, we let guest own most CR4 bit. Which means guest handles whether the CR4 writting is invalid or not and GP injection if it's invalid writing. Two bits are exception here: we filter VMX and PCID feature to guest (which means they are supported on native). So we can't depends on guest to inject GP for these bits. Instead, we should explicitly trap these CR4 bits update and inject GP to guest from HV. Signed-off-by: Yin Fengwei <fengwei.yin@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>		2018-08-01 11:35:30 +08:00
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arch/x86	hv: Explicitly trap VMXE and PCIDE bit for CR4 write	2018-08-01 11:35:30 +08:00
common	HV: io: add post-work for PCICFG and WP requests	2018-07-31 10:22:03 +08:00
debug	hv:Delete serial files	2018-07-30 16:25:16 +08:00
lib	HV: Rename functions beginning with "_"	2018-07-30 10:11:54 +08:00
public	HV: io: refine state transitions of VHM requests	2018-07-31 10:22:03 +08:00
hv_debug.h	hv:Reshuffle console/uart code	2018-07-30 16:25:16 +08:00
hv_lib.h	license: Replace license text with SPDX tag	2018-06-01 10:43:06 +08:00
hypervisor.h	hv: mmu: revisit mmu modify page table attributes	2018-07-19 11:11:32 +08:00