Sainath Grandhi 1bf3163d08 hv: Hypervisor access to PCI devices with 64-bit MMIO BARs ... PCI devices with 64-bit MMIO BARs and requiring large MMIO space can be assigned with physical address range at the very high end of platform supported physical address space. This patch uses the board info for 64-bit MMIO window as programmed by BIOS and constructs 1G page tables for the same. As ACRN uses identity mapping from Linear to Physical address space physical addresses upto 48 bit or 256TB can be supported. Tracked-On: #4586 Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>		2020-04-15 10:54:39 +08:00
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x86	hv: Hypervisor access to PCI devices with 64-bit MMIO BARs	2020-04-15 10:54:39 +08:00