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For platform with HLAT (Hypervisor-managed Linear Address Translation) capability, the hypervisor shall hide this feature to its guest. This patch adds MSR_IA32_VMX_PROCBASED_CTLS3 MSR to unsupported MSR list. The presence of this MSR is determined by 1-setting of bit 49 of MSR MSR_IA32_VMX_PROCBASED_CTLS. which is already in unsupported MSR list. [2] Related documentations: [1] Intel Architecture Instruction Set Extensions, version Feb 16, 2021, Ch 6.12 [2] Intel KeyLocker Specification, Sept 2020, Ch 7.2 Tracked-On: #5895 Signed-off-by: Yifan Liu <yifan1.liu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com> |
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| .. | ||
| assign.c | ||
| ept.c | ||
| guest_memory.c | ||
| hyperv.c | ||
| instr_emul.c | ||
| pm.c | ||
| splitlock.c | ||
| trusty.c | ||
| ucode.c | ||
| vcpu.c | ||
| vcpuid.c | ||
| ve820.c | ||
| virq.c | ||
| virtual_cr.c | ||
| vlapic_priv.h | ||
| vlapic.c | ||
| vm_reset.c | ||
| vm.c | ||
| vmcall.c | ||
| vmcs.c | ||
| vmexit.c | ||
| vmsr.c | ||
| vmtrr.c | ||
| vmx_asm.S | ||
| vmx_io.c | ||