Wei6 Zhang 763c6684e3 misc: Remove AVAILABLE_IRQ_INFO values from RISC-V board XML ...

Clear AVAILABLE_IRQ_INFO content in qemu-riscv.xml as the x86 ISA IRQ
values (3, 4, 5, 6, 7, 8, 9, 11) are not applicable to RISC-V architecture.

Note: This leaves AVAILABLE_IRQ_INFO empty as a placeholder. A proper
RISC-V implementation should populate this field and fill the device
tree for VM.

Tracked-On: #8814
Reviewed-by: Fei Li <fei1.li@intel.com>
Signed-off-by: Wei6 Zhang <wei6.zhang@intel.com>

2025-10-09 16:15:09 +08:00

..

adl-asrock

misc: update ASRock board XML

2022-11-04 12:14:50 +08:00

cfl-k700-i7

config-tools: change 'DISABLED' settings to 'ENABLED' in config xml

2022-08-17 09:23:33 +08:00

generic_board

hv: sched: Add sched_params struct for thread parameters

2023-09-18 16:26:05 +08:00

nuc11tnbi5

config-tools: change 'DISABLED' settings to 'ENABLED' in config xml

2022-08-17 09:23:33 +08:00

qemu

config-tools: change 'DISABLED' settings to 'ENABLED' in config xml

2022-08-17 09:23:33 +08:00

qemu-riscv

misc: Remove AVAILABLE_IRQ_INFO values from RISC-V board XML

2025-10-09 16:15:09 +08:00

tgl-vecow-spc-7100-Corei7

config-tools: change 'DISABLED' settings to 'ENABLED' in config xml

2022-08-17 09:23:33 +08:00

whl-ipc-i5

config-tools: change 'DISABLED' settings to 'ENABLED' in config xml

2022-08-17 09:23:33 +08:00

__init__.py

config_tools: refactor configurator for web page cache issue

2022-04-25 18:13:12 +08:00

sample_launch_scripts

misc: Update sample launch scripts into generic_board folder.

2022-11-21 11:51:33 +08:00