Li Fei1 4367657771 hv: vpci: add a global CFG header configuration access handler ...

Add cfg_header_read_cfg and cfg_header_write_cfg to handle the 1st 64B
CFG Space header PCI configuration space.
Only Command and Status Registers are pass through;
Only Command and Status Registers and Base Address Registers are writable.
In order to implement this, we add two type bit mask for per 4B register:
pass through mask and read-only mask. When pass through bit mask is set, this
means this bit of this 4B register is pass through, otherwise, it is virtualized;
When read-only mask is set, this means this bit of this 4B register is read-only,
otherwise, it's writable. We should write it to physical CFG space or virtual
CFG space base on whether the pass through bit mask is set or not.

Tracked-On: #4371
Signed-off-by: Li Fei1 <fei1.li@intel.com>

2020-03-06 14:08:04 +08:00

..

pci.h

hv: vpci: add a global CFG header configuration access handler

2020-03-06 14:08:04 +08:00