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1) In x2apic mode, when read ICR, we want to read a 64-bits value. 2) In x2apic mode, write self-IPI will trap out through MSR write when VID isn't enabled. Tracked-On: #1842 Signed-off-by: Li, Fei1 <fei1.li@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>