Victor Sun 4c0965d89e HV: correct ept page array usage ... Currently ept_pages_info[] is initialized with first element only that force VM of id 0 using SOS EPT pages. This is incorrect for logical partition and hybrid scenario. Considering SOS_RAM_SIZE and UOS_RAM_SIZE are configured separately, we should use different ept pages accordingly. So, the PRE_VM_NUM/SOS_VM_NUM and MAX_POST_VM_NUM macros are introduced to resolve this issue. The macros would be generated by acrn-config tool when user configure ACRN for their specific scenario. One more thing, that when UOS_RAM_SIZE is less then 2GB, the EPT address range should be (4G + PLATFORM_HI_MMIO_SIZE). Tracked-On: #4458 Signed-off-by: Victor Sun <victor.sun@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>		2020-03-12 14:56:34 +08:00
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arch/x86	HV: correct ept page array usage	2020-03-12 14:56:34 +08:00
common	hv: Variable/macro renaming for intr handling of PT devices using IO-APIC/PIC	2020-03-06 11:29:02 +08:00
debug	HV: correct ept page array usage	2020-03-12 14:56:34 +08:00
dm	hv: refine naming	2020-03-11 08:35:30 +08:00
hw	hv: vpci: pass through stolen memory and opregion memory for GVT-D	2020-03-11 10:59:23 +08:00
lib	hv: support xsave in context switch	2019-12-02 09:31:12 +08:00
public	hv: vPCI: remove passthrough PCI device unuse code	2020-02-24 16:17:38 +08:00