mirror of
https://github.com/projectacrn/acrn-hypervisor.git
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38b9b7d37c
Now the Intel RDT emulation is working in progress. So disable it for temporary solution to avoid guest OS running with incorrect RDT configuration. Signed-off-by: Shuo Liu <shuo.a.liu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
140 lines
4.3 KiB
C
140 lines
4.3 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* cpuid.h
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*
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* Created on: Jan 4, 2018
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* Author: don
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*/
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#ifndef CPUID_H_
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#define CPUID_H_
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/* CPUID bit definitions */
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#define CPUID_ECX_SSE3 (1U<<0U)
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#define CPUID_ECX_PCLMUL (1U<<1U)
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#define CPUID_ECX_DTES64 (1U<<2U)
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#define CPUID_ECX_MONITOR (1U<<3U)
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#define CPUID_ECX_DS_CPL (1U<<4U)
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#define CPUID_ECX_VMX (1U<<5U)
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#define CPUID_ECX_SMX (1U<<6U)
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#define CPUID_ECX_EST (1U<<7U)
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#define CPUID_ECX_TM2 (1U<<8U)
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#define CPUID_ECX_SSSE3 (1U<<9U)
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#define CPUID_ECX_CID (1U<<10U)
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#define CPUID_ECX_FMA (1U<<12U)
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#define CPUID_ECX_CX16 (1U<<13U)
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#define CPUID_ECX_ETPRD (1U<<14U)
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#define CPUID_ECX_PDCM (1U<<15U)
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#define CPUID_ECX_DCA (1U<<18U)
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#define CPUID_ECX_SSE4_1 (1U<<19U)
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#define CPUID_ECX_SSE4_2 (1U<<20U)
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#define CPUID_ECX_x2APIC (1U<<21U)
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#define CPUID_ECX_MOVBE (1U<<22U)
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#define CPUID_ECX_POPCNT (1U<<23U)
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#define CPUID_ECX_AES (1U<<25U)
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#define CPUID_ECX_XSAVE (1U<<26U)
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#define CPUID_ECX_OSXSAVE (1U<<27U)
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#define CPUID_ECX_AVX (1U<<28U)
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#define CPUID_EDX_FPU (1U<<0U)
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#define CPUID_EDX_VME (1U<<1U)
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#define CPUID_EDX_DE (1U<<2U)
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#define CPUID_EDX_PSE (1U<<3U)
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#define CPUID_EDX_TSC (1U<<4U)
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#define CPUID_EDX_MSR (1U<<5U)
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#define CPUID_EDX_PAE (1U<<6U)
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#define CPUID_EDX_MCE (1U<<7U)
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#define CPUID_EDX_CX8 (1U<<8U)
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#define CPUID_EDX_APIC (1U<<9U)
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#define CPUID_EDX_SEP (1U<<11U)
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#define CPUID_EDX_MTRR (1U<<12U)
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#define CPUID_EDX_PGE (1U<<13U)
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#define CPUID_EDX_MCA (1U<<14U)
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#define CPUID_EDX_CMOV (1U<<15U)
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#define CPUID_EDX_PAT (1U<<16U)
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#define CPUID_EDX_PSE36 (1U<<17U)
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#define CPUID_EDX_PSN (1U<<18U)
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#define CPUID_EDX_CLF (1U<<19U)
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#define CPUID_EDX_DTES (1U<<21U)
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#define CPUID_EDX_ACPI (1U<<22U)
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#define CPUID_EDX_MMX (1U<<23U)
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#define CPUID_EDX_FXSR (1U<<24U)
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#define CPUID_EDX_SSE (1U<<25U)
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#define CPUID_EDX_SSE2 (1U<<26U)
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#define CPUID_EDX_SS (1U<<27U)
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#define CPUID_EDX_HTT (1U<<28U)
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#define CPUID_EDX_TM1 (1U<<29U)
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#define CPUID_EDX_IA64 (1U<<30U)
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#define CPUID_EDX_PBE (1U<<31U)
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/* CPUID.07H:EBX.TSC_ADJUST*/
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#define CPUID_EBX_TSC_ADJ (1U<<1U)
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/* CPUID.07H:EDX.IBRS_IBPB*/
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#define CPUID_EDX_IBRS_IBPB (1U<<26U)
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/* CPUID.07H:EDX.STIBP*/
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#define CPUID_EDX_STIBP (1U<<27U)
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/* CPUID.80000001H:EDX.Page1GB*/
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#define CPUID_EDX_PAGE1GB (1U<<26U)
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/* CPUID.07H:EBX.INVPCID*/
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#define CPUID_EBX_INVPCID (1U<<10U)
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/* CPUID.07H:EBX.PQM */
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#define CPUID_EBX_PQM (1U<<12U)
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/* CPUID.07H:EBX.PQE */
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#define CPUID_EBX_PQE (1U<<15U)
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/* CPUID.01H:ECX.PCID*/
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#define CPUID_ECX_PCID (1U<<17U)
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/* CPUID source operands */
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#define CPUID_VENDORSTRING 0U
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#define CPUID_FEATURES 1U
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#define CPUID_TLB 2U
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#define CPUID_SERIALNUM 3U
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#define CPUID_EXTEND_FEATURE 7U
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#define CPUID_MAX_EXTENDED_FUNCTION 0x80000000U
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#define CPUID_EXTEND_FUNCTION_1 0x80000001U
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#define CPUID_EXTEND_FUNCTION_2 0x80000002U
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#define CPUID_EXTEND_FUNCTION_3 0x80000003U
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#define CPUID_EXTEND_FUNCTION_4 0x80000004U
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#define CPUID_EXTEND_ADDRESS_SIZE 0x80000008U
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static inline void __cpuid(uint32_t *eax, uint32_t *ebx,
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uint32_t *ecx, uint32_t *edx)
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{
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/* Execute CPUID instruction and save results */
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asm volatile("cpuid":"=a"(*eax), "=b"(*ebx),
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"=c"(*ecx), "=d"(*edx)
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: "0" (*eax), "2" (*ecx)
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: "memory");
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}
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static inline void cpuid(uint32_t leaf,
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uint32_t *eax, uint32_t *ebx,
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uint32_t *ecx, uint32_t *edx)
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{
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*eax = leaf;
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*ecx = 0U;
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__cpuid(eax, ebx, ecx, edx);
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}
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static inline void cpuid_subleaf(uint32_t leaf, uint32_t subleaf,
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uint32_t *eax, uint32_t *ebx,
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uint32_t *ecx, uint32_t *edx)
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{
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*eax = leaf;
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*ecx = subleaf;
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__cpuid(eax, ebx, ecx, edx);
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}
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int set_vcpuid_entries(struct vm *vm);
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void guest_cpuid(struct vcpu *vcpu,
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uint32_t *eax, uint32_t *ebx,
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uint32_t *ecx, uint32_t *edx);
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#endif /* CPUID_H_ */
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