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This patch adds interrupt pin related information into the board XML, including: * The PCI routing table in ACPI DSDT/SSDT are parsed and generated into the board XML as "interrupt_pin_routing" nodes. * IRQs encoded in _CRS directly are represented as resources of type "irq". * Interrupt lines (i.e. INTx#) of PCI devices are represented as resources of type "interrupt_pin". When the PCI routing table is available, the corresponding interrupt line is identified and represented as the "source" attribute of the resource node. Due to the existence of vIOAPIC in ACRN VMs, the board inspector interprets the \_PIC method with parameter 1 to inform the ACPI namespace that the interrupt model should be in APIC mode. v1 -> v2: * Remove the msi_enable variable which is defined but never used. Tracked-On: #6287 Signed-off-by: Junjie Mao <junjie.mao@intel.com> |
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.. | ||
lib | ||
bdf.py | ||
cpu_affinity.py | ||
gpa.py | ||
hv_ram.py | ||
intx.py | ||
main.py | ||
pio.py |