Zide Chen 5cbe079e24 hv: MSI-X Message Address write fix ...

Some PCI devices can not accept DWORD write to the MSI-X Table though
PCI Spec allows it:

PCI Spec 3.0 6.8.3.2 MSI-X Configuration: Specifically, software is
always permitted to fill in the Message Address and Message Upper Address
fields with a single QWORD write.

Tracked-On: #1568
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>

2018-11-01 21:22:10 +08:00

..

hw

hv: Don't check multi-function flag in PCI enumeration

2018-11-01 21:22:10 +08:00

vpci

hv: MSI-X Message Address write fix

2018-11-01 21:22:10 +08:00

vioapic.c

hv: rework the MMIO handler callback hv_mem_io_handler_t arguments

2018-10-29 14:29:37 +08:00

vpic.c

hv: fix integer violations

2018-10-31 15:01:57 +08:00

vrtc.c

hv: merge hv_lib.h and hypervisor.h

2018-09-27 15:55:41 +08:00