Li, Fei1 5d6c9c33ca hv: vlapic: clear up where needs atomic operation in vLAPIC ... In almost case, vLAPIC will only be accessed by the related vCPU. There's no synchronization issue in this case. However, other vCPUs could deliver interrupts to the current vCPU, in this case, the IRR (for APICv base situation) or PIR (for APICv advanced situation) and TMR for both cases could be accessed by more than one vCPUS simultaneously. So operations on IRR or PIR should be atomical and visible to other vCPUs immediately. In another case, vLAPIC could be accessed by another vCPU when create vCPU or reset vCPU which could be supposed to be consequently. Tracked-On: #1842 Signed-off-by: Li, Fei1 <fei1.li@intel.com>		2019-07-11 09:15:47 +08:00
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x86	hv: vlapic: clear up where needs atomic operation in vLAPIC	2019-07-11 09:15:47 +08:00