Li Fei1 628bca5cad hv: pgtable: use new algo to calculate PPT/EPT_PD_PAGE_NUM ... In order to support platform (such as Ander Lake) which physical address width bits is 46, the current code need to reserve 2^16 PD page ((2^46) / (2^30)). This is a complete waste of memory. This patch would reserve PD page by three parts: 1. DRAM - may take PD_PAGE_NUM(CONFIG_PLATFORM_RAM_SIZE) PD pages at most; 2. low MMIO - may take PD_PAGE_NUM(MEM_1G << 2U) PD pages at most; 3. high MMIO - may takes (CONFIG_MAX_PCI_DEV_NUM * 6U) PD pages (may plus PDPT entries if its size is larger than 1GB ) at most for: (a) MMIO BAR size must be a power of 2 from 16 bytes; (b) MMIO BAR base address must be power of two in size and are aligned with its size. Tracked-On: #5929 Signed-off-by: Li Fei1 <fei1.li@intel.com>		2021-04-22 14:35:57 +08:00
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x86	hv: pgtable: use new algo to calculate PPT/EPT_PD_PAGE_NUM	2021-04-22 14:35:57 +08:00