Li Fei1 ae4fa40adc hv: vpci: hv: vpci: refine pci device assignment logic ... Now Host Bridge and PCI Bridge could only be added to SOS's acrn_vm_pci_dev_config. So For UOS, we always emualte Host Bridge and PCI Bridge for it and assign PCI device to it; for SOS, if it's the highest severity VM, we will assign Host Bridge and PCI Bridge to it directly, otherwise, we will emulate them same as UOS. Tracked-On: #4550 Signed-off-by: Li Fei1 <fei1.li@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>		2020-06-03 22:00:43 +08:00
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arch/x86	hv: vpci: hv: vpci: refine pci device assignment logic	2020-06-03 22:00:43 +08:00
common	hv: ptirq: refine find_ptirq_entry by hashing	2020-05-20 16:04:16 +08:00
debug	HV: correct ept page array usage	2020-03-12 14:56:34 +08:00
dm	hv: vpci: refine vpci deinit	2020-05-13 14:31:01 +08:00
hw	hv: pci: check whether a PCI device is host bridge or not by class	2020-06-03 22:00:43 +08:00
lib	hv: ptirq: refine find_ptirq_entry by hashing	2020-05-20 16:04:16 +08:00
public	hv: dynamically configure CPU affinity through hypercall	2020-04-23 09:38:54 +08:00