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b8f151a55f
According PCI Code and ID Assignment Specification Revision 1.11, a PCI device whose Base Class is 06h and Sub-Class is 00h is a Host bridge. Tracked-On: #4550 Signed-off-by: Li Fei1 <fei1.li@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
383 lines
11 KiB
C
383 lines
11 KiB
C
/*-
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* Copyright (c) 1997, Stefan Esser <se@freebsd.org>
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* Copyright (c) 2011 NetApp, Inc.
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* Copyright (c) 2018 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef PCI_H_
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#define PCI_H_
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/*
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* PCIM_xxx: mask to locate subfield in register
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* PCIR_xxx: config register offset
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* PCIC_xxx: device class
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* PCIS_xxx: device subclass
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* PCIP_xxx: device programming interface
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* PCIV_xxx: PCI vendor ID (only required to fixup ancient devices)
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* PCID_xxx: device ID
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* PCIY_xxx: capability identification number
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* PCIZ_xxx: extended capability identification number
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*/
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#define PCI_CFG_HEADER_LENGTH 0x40U
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/* some PCI bus constants */
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#define PCI_BUSMAX 0xFFU
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#define PCI_SLOTMAX 0x1FU
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#define PCI_FUNCMAX 0x7U
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#define PCI_BAR_COUNT 0x6U
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#define PCI_REGMASK 0xFCU
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#define PCI_CONFIG_SPACE_SIZE 0x100U
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#define PCIE_CONFIG_SPACE_SIZE 0x1000U
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#define PCI_MMCONFIG_SIZE 0x10000000U
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/* I/O ports */
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#define PCI_CONFIG_ADDR 0xCF8U
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#define PCI_CONFIG_DATA 0xCFCU
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#define PCI_CFG_ENABLE 0x80000000U
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/* PCI config header registers for all devices */
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#define PCIR_VENDOR 0x00U
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#define PCIR_DEVICE 0x02U
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#define PCIR_COMMAND 0x04U
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#define PCIM_CMD_PORTEN 0x01U
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#define PCIM_CMD_MEMEN 0x02U
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#define PCIM_CMD_INTxDIS 0x400U
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#define PCIR_STATUS 0x06U
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#define PCIM_STATUS_CAPPRESENT 0x0010U
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#define PCIR_REVID 0x08U
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#define PCIR_SUBCLASS 0x0AU
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#define PCIR_CLASS 0x0BU
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#define PCIR_HDRTYPE 0x0EU
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#define PCIM_HDRTYPE 0x7FU
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#define PCIM_HDRTYPE_NORMAL 0x00U
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#define PCIM_HDRTYPE_BRIDGE 0x01U
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#define PCIM_HDRTYPE_CARDBUS 0x02U
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#define PCIM_MFDEV 0x80U
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#define PCIR_BARS 0x10U
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#define PCIM_BAR_SPACE 0x01U
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#define PCIM_BAR_IO_SPACE 0x01U
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#define PCIM_BAR_MEM_TYPE 0x06U
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#define PCIM_BAR_MEM_32 0x00U
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#define PCIM_BAR_MEM_1MB 0x02U
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#define PCIM_BAR_MEM_64 0x04U
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#define PCIM_BAR_MEM_BASE 0xFFFFFFF0U
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#define PCIV_SUB_VENDOR_ID 0x2CU
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#define PCIR_CAP_PTR 0x34U
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#define PCIR_CAP_PTR_CARDBUS 0x14U
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#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
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#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
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#define PCIR_INTERRUPT_LINE 0x3cU
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#define PCIR_INTERRUPT_PIN 0x3dU
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/* config registers for header type 1 (PCI-to-PCI bridge) devices */
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#define PCIR_PRIBUS_1 0x18U
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#define PCIR_SECBUS_1 0x19U
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#define PCIR_SUBBUS_1 0x1AU
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/* Capability Register Offsets */
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#define PCICAP_ID 0x0U
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#define PCICAP_NEXTPTR 0x1U
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/* Capability Identification Numbers */
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#define PCIY_MSI 0x05U
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#define PCIY_MSIX 0x11U
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/* PCIe Extended Capability*/
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#define PCI_ECAP_BASE_PTR 0x100U
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#define PCI_ECAP_ID(hdr) ((uint32_t)((hdr) & 0xFFFFU))
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#define PCI_ECAP_NEXT(hdr) ((uint32_t)(((hdr) >> 20U) & 0xFFCU))
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#define PCIZ_SRIOV 0x10U
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/* SRIOV Definitions */
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#define PCI_SRIOV_CAP_LEN 0x40U
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#define PCIR_SRIOV_CONTROL 0x8U
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#define PCIR_SRIOV_TOTAL_VFS 0xEU
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#define PCIR_SRIOV_NUMVFS 0x10U
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#define PCIR_SRIOV_FST_VF_OFF 0x14U
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#define PCIR_SRIOV_VF_STRIDE 0x16U
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#define PCIR_SRIOV_VF_DEV_ID 0x1AU
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#define PCIR_SRIOV_VF_BAR_OFF 0x24U
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#define PCIM_SRIOV_VF_ENABLE 0x1U
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/* PCI Message Signalled Interrupts (MSI) */
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#define PCIR_MSI_CTRL 0x02U
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#define PCIM_MSICTRL_64BIT 0x80U
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#define PCIM_MSICTRL_MSI_ENABLE 0x01U
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#define PCIR_MSI_ADDR 0x4U
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#define PCIR_MSI_ADDR_HIGH 0x8U
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#define PCIR_MSI_DATA 0x8U
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#define PCIR_MSI_DATA_64BIT 0xCU
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#define PCIR_MSI_MASK 0x10U
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#define PCIM_MSICTRL_MMC_MASK 0x000EU
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#define PCIM_MSICTRL_MME_MASK 0x0070U
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/* PCI device class */
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#define PCIC_BRIDGE 0x06U
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#define PCIS_BRIDGE_HOST 0x00U
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/* PCI device subclass */
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#define PCIS_BRIDGE_PCI 0x04U
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/* MSI-X definitions */
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#define PCIR_MSIX_CTRL 0x2U
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#define PCIR_MSIX_TABLE 0x4U
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#define PCIR_MSIX_PBA 0x8U
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#define PCIM_MSIXCTRL_MSIX_ENABLE 0x8000U
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#define PCIM_MSIXCTRL_FUNCTION_MASK 0x4000U
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#define PCIM_MSIXCTRL_TABLE_SIZE 0x07FFU
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#define PCIM_MSIX_BIR_MASK 0x7U
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#define PCIM_MSIX_VCTRL_MASK 0x1U
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#define MSIX_CAPLEN 12U
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#define MSIX_TABLE_ENTRY_SIZE 16U
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/* PCI Power Management Capability */
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#define PCIY_PMC 0x01U
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/* Power Management Control/Status Register */
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#define PCIR_PMCSR 0x04U
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#define PCIM_PMCSR_NO_SOFT_RST (0x1U << 3U)
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/* PCI Express Capability */
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#define PCIY_PCIE 0x10U
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#define PCIR_PCIE_DEVCAP 0x04U
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#define PCIR_PCIE_DEVCTRL 0x08U
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#define PCIM_PCIE_FLRCAP (0x1U << 28U)
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#define PCIM_PCIE_FLR (0x1U << 15U)
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#define PCIR_PCIE_DEVCAP2 0x24U
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#define PCIM_PCIE_DEVCAP2_ARI (0x1U << 5U)
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#define PCIR_PCIE_DEVCTL2 0x28U
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#define PCIM_PCIE_DEVCTL2_ARI (0x1U << 5U)
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/* Conventional PCI Advanced Features Capability */
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#define PCIY_AF 0x13U
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#define PCIM_AF_FLR_CAP (0x1U << 25U)
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#define PCIR_AF_CTRL 0x4U
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#define PCIM_AF_FLR 0x1U
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#define PCI_STD_NUM_BARS 6U
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union pci_bdf {
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uint16_t value;
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struct {
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uint8_t f : 3; /* BITs 0-2 */
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uint8_t d : 5; /* BITs 3-7 */
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uint8_t b; /* BITs 8-15 */
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} bits;
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struct {
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uint8_t devfun; /* BITs 0-7 */
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uint8_t bus; /* BITs 8-15 */
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} fields;
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};
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enum pci_bar_type {
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PCIBAR_NONE = 0,
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PCIBAR_IO_SPACE,
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PCIBAR_MEM32,
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PCIBAR_MEM64,
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PCIBAR_MEM64HI,
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};
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/* Basic MSIX capability info */
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struct pci_msix_cap {
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uint32_t capoff;
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uint32_t caplen;
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uint8_t table_bar;
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uint32_t table_offset;
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uint32_t table_count;
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uint8_t cap[MSIX_CAPLEN];
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};
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struct pci_sriov_cap {
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uint32_t capoff;
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uint32_t caplen;
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};
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struct pci_pdev {
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uint8_t hdr_type;
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uint8_t base_class;
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uint8_t sub_class;
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/* IOMMU responsible for DMA and Interrupt Remapping for this device */
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uint32_t drhd_index;
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/* The bar info of the physical PCI device. */
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uint32_t nr_bars; /* 6 for normal device, 2 for bridge, 1 for cardbus */
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uint32_t bars[PCI_STD_NUM_BARS];
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/* The bus/device/function triple of the physical PCI device. */
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union pci_bdf bdf;
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uint32_t msi_capoff;
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uint32_t pcie_capoff;
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struct pci_msix_cap msix;
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struct pci_sriov_cap sriov;
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bool has_pm_reset;
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bool has_flr;
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bool has_af_flr;
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};
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struct pci_cfg_ops {
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uint32_t (*pci_read_cfg)(union pci_bdf bdf, uint32_t offset, uint32_t bytes);
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void (*pci_write_cfg)(union pci_bdf bdf, uint32_t offset, uint32_t bytes, uint32_t val);
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};
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static inline bool is_host_bridge(const struct pci_pdev *pdev)
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{
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return (pdev->base_class == PCIC_BRIDGE) && (pdev->sub_class == PCIS_BRIDGE_HOST);
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}
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static inline bool is_bridge(const struct pci_pdev *pdev)
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{
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return pdev->hdr_type == PCIM_HDRTYPE_BRIDGE;
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}
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static inline uint32_t pci_bar_offset(uint32_t idx)
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{
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return PCIR_BARS + (idx << 2U);
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}
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static inline uint32_t pci_bar_index(uint32_t offset)
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{
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return (offset - PCIR_BARS) >> 2U;
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}
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static inline bool is_bar_offset(uint32_t nr_bars, uint32_t offset)
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{
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bool ret;
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if ((offset >= pci_bar_offset(0U))
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&& (offset < pci_bar_offset(nr_bars))) {
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ret = true;
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} else {
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ret = false;
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}
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return ret;
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}
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static inline enum pci_bar_type pci_get_bar_type(uint32_t val)
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{
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enum pci_bar_type type = PCIBAR_NONE;
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if ((val & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE) {
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type = PCIBAR_IO_SPACE;
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} else {
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switch (val & PCIM_BAR_MEM_TYPE) {
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case PCIM_BAR_MEM_32:
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type = PCIBAR_MEM32;
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break;
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case PCIM_BAR_MEM_64:
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type = PCIBAR_MEM64;
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break;
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default:
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/*no actions are required for other cases.*/
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break;
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}
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}
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return type;
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}
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static inline bool bdf_is_equal(union pci_bdf a, union pci_bdf b)
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{
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return (a.value == b.value);
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}
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#ifdef CONFIG_ACPI_PARSE_ENABLED
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void set_mmcfg_base(uint64_t mmcfg_base);
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#endif
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uint64_t get_mmcfg_base(void);
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struct pci_pdev *init_pdev(uint16_t pbdf, uint32_t drhd_index);
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uint32_t pci_pdev_read_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes);
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void pci_pdev_write_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes, uint32_t val);
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void enable_disable_pci_intx(union pci_bdf bdf, bool enable);
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/*
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* @brief Walks the PCI heirarchy and initializes array of pci_pdev structs
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* Uses DRHD info from ACPI DMAR tables to cover the endpoints and
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* bridges along with their hierarchy captured in the device scope entries
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* Walks through rest of the devices starting at bus 0 and thru PCI_BUSMAX
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*/
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void init_pci_pdev_list(void);
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/* @brief: Find the DRHD index corresponding to a PCI device
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* Runs through the pci_pdev_array and returns the value in drhd_idx
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* member from pdev strucutre that matches matches B:D.F
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*
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* @pbdf[in] B:D.F of a PCI device
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*
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* @return if there is a matching pbdf in pci_pdev_array, pdev->drhd_idx, else -1U
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*/
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uint32_t pci_lookup_drhd_for_pbdf(uint16_t pbdf);
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static inline bool is_pci_vendor_valid(uint32_t vendor_id)
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{
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return !((vendor_id == 0xFFFFFFFFU) || (vendor_id == 0U) ||
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(vendor_id == 0xFFFF0000U) || (vendor_id == 0xFFFFU));
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}
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static inline uint32_t read_pci_pdev_cfg_vendor(union pci_bdf pbdf)
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{
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return pci_pdev_read_cfg(pbdf, PCIR_VENDOR, 2U);
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}
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static inline uint8_t read_pci_pdev_cfg_headertype(union pci_bdf pbdf)
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{
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return (uint8_t)pci_pdev_read_cfg(pbdf, PCIR_HDRTYPE, 1U);
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}
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static inline uint8_t read_pci_pdev_cfg_secbus(union pci_bdf pbdf)
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{
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return (uint8_t)pci_pdev_read_cfg(pbdf, PCIR_SECBUS_1, 1U);
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}
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static inline bool is_pci_cfg_multifunction(uint8_t header_type)
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{
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return ((header_type & PCIM_MFDEV) == PCIM_MFDEV);
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}
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static inline bool is_pci_cfg_bridge(uint8_t header_type)
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{
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return ((header_type & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE);
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}
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bool is_plat_hidden_pdev(union pci_bdf bdf);
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bool pdev_need_bar_restore(const struct pci_pdev *pdev);
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void pdev_restore_bar(const struct pci_pdev *pdev);
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void pci_switch_to_mmio_cfg_ops(void);
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#endif /* PCI_H_ */
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