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6e77a8d5f1
For data structure types "enum vpic_wire_mode, struct stack_canary", its name is identical with variable name in the same scope. This MISRA C violation is detected by static analysis tool. For variables "segment_override, pde_index", its name is identical with function name. This MISRA C violation is detected. Naming convention rule:Variable name can be shortened from its data structure type name. The following udpates are made: enum vpic_wire_mode vpic_wire_mode-->enum vpic_wire_mode wire_mode struct stack_canary stack_canary-->struct stack_canary stk_canary uint8_t segment_override:1 --> uint8_t seg_override:1 uint32_t pde_index--> uint32_t pde_idx V1-->V2: Remove update "enum cpu_state cpu_state-->enum cpu_state state" and "enum irqstate irqstate-->enum irq_ops_mode ops_mode", other patch will cover it. V2-->V3: Update "uint32_t pde_index--> uint32_t pde_idx". Signed-off-by: Xiangyang Wu <xiangyang.wu@linux.intel.com>
259 lines
8.1 KiB
C
259 lines
8.1 KiB
C
/*-
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* Copyright (c) 2012 NetApp, Inc.
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* Copyright (c) 2017 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef INSTR_EMUL_WRAPPER_H
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#define INSTR_EMUL_WRAPPER_H
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#include <cpu.h>
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/**
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*
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* Identifiers for architecturally defined registers.
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*
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* These register names is used in condition statement.
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* Within the following groups,register name need to be
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* kept in order:
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* General register names group (CPU_REG_RAX~CPU_REG_R15);
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* Non general register names group (CPU_REG_CR0~CPU_REG_GDTR);
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* Segement register names group (CPU_REG_ES~CPU_REG_GS).
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*/
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enum cpu_reg_name {
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/* General purpose register layout should align with
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* struct cpu_gp_regs
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*/
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CPU_REG_RAX,
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CPU_REG_RCX,
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CPU_REG_RDX,
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CPU_REG_RBX,
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CPU_REG_RSP,
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CPU_REG_RBP,
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CPU_REG_RSI,
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CPU_REG_RDI,
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CPU_REG_R8,
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CPU_REG_R9,
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CPU_REG_R10,
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CPU_REG_R11,
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CPU_REG_R12,
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CPU_REG_R13,
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CPU_REG_R14,
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CPU_REG_R15,
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CPU_REG_CR0,
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CPU_REG_CR2,
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CPU_REG_CR3,
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CPU_REG_CR4,
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CPU_REG_DR7,
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CPU_REG_RIP,
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CPU_REG_RFLAGS,
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/*CPU_REG_NATURAL_LAST*/
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CPU_REG_EFER,
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CPU_REG_PDPTE0,
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CPU_REG_PDPTE1,
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CPU_REG_PDPTE2,
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CPU_REG_PDPTE3,
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/*CPU_REG_64BIT_LAST,*/
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CPU_REG_ES,
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CPU_REG_CS,
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CPU_REG_SS,
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CPU_REG_DS,
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CPU_REG_FS,
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CPU_REG_GS,
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CPU_REG_LDTR,
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CPU_REG_TR,
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CPU_REG_IDTR,
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CPU_REG_GDTR
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/*CPU_REG_LAST*/
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};
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/**
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* Define the following MACRO to make range checking clear.
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*
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* CPU_REG_FIRST indicates the first register name, its value
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* is the same as CPU_REG_RAX;
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* CPU_REG_LAST indicates the last register name, its value is
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* the same as CPU_REG_GDTR;
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*
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* CPU_REG_GENERAL_FIRST indicates the first general register name,
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* its value is the same as CPU_REG_RAX;
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* CPU_REG_GENERAL_LAST indicates the last general register name,
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* its value is the same as CPU_REG_RDI;
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*
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* CPU_REG_NONGENERAL_FIRST indicates the first non general register
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* name, its value is the same as CPU_REG_CR0;
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* CPU_REG_NONGENERAL_LAST indicates the last non general register
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* name, its value is the same as CPU_REG_GDTR;
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*
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* CPU_REG_NATURAL_FIRST indicates the first register name that
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* is corresponds to the natural width field in VMCS, its value
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* is the same as CPU_REG_CR0;
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* CPU_REG_NATURAL_LAST indicates the last register name that
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* is corresponds to the natural width field in VMCS, its value
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* is the same as CPU_REG_RFLAGS;
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*
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* CPU_REG_64BIT_FIRST indicates the first register name that
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* is corresponds to the 64 bit field in VMCS, its value
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* is the same as CPU_REG_EFER;
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* CPU_REG_64BIT_LAST indicates the last register name that
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* is corresponds to the 64 bit field in VMCS, its value
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* is the same as CPU_REG_PDPTE3;
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*
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* CPU_REG_SEG_FIRST indicates the first segement register name,
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* its value is the same as CPU_REG_ES;
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* CPU_REG_SEG_FIRST indicates the last segement register name,
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* its value is the same as CPU_REG_GS
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*
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*/
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#define CPU_REG_FIRST CPU_REG_RAX
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#define CPU_REG_LAST CPU_REG_GDTR
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#define CPU_REG_GENERAL_FIRST CPU_REG_RAX
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#define CPU_REG_GENERAL_LAST CPU_REG_R15
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#define CPU_REG_NONGENERAL_FIRST CPU_REG_CR0
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#define CPU_REG_NONGENERAL_LAST CPU_REG_GDTR
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#define CPU_REG_NATURAL_FIRST CPU_REG_CR0
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#define CPU_REG_NATURAL_LAST CPU_REG_RFLAGS
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#define CPU_REG_64BIT_FIRST CPU_REG_EFER
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#define CPU_REG_64BIT_LAST CPU_REG_PDPTE3
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#define CPU_REG_SEG_FIRST CPU_REG_ES
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#define CPU_REG_SEG_LAST CPU_REG_GS
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struct instr_emul_vie_op {
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uint8_t op_byte; /* actual opcode byte */
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uint8_t op_type; /* type of operation (e.g. MOV) */
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uint16_t op_flags;
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};
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#define VIE_INST_SIZE 15U
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struct instr_emul_vie {
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uint8_t inst[VIE_INST_SIZE]; /* instruction bytes */
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uint8_t num_valid; /* size of the instruction */
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uint8_t num_processed;
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uint8_t addrsize:4, opsize:4; /* address and operand sizes */
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uint8_t rex_w:1, /* REX prefix */
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rex_r:1,
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rex_x:1,
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rex_b:1,
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rex_present:1,
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repz_present:1, /* REP/REPE/REPZ prefix */
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repnz_present:1, /* REPNE/REPNZ prefix */
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opsize_override:1, /* Operand size override */
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addrsize_override:1, /* Address size override */
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seg_override:1; /* Segment override */
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uint8_t mod:2, /* ModRM byte */
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reg:4,
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rm:4;
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uint8_t ss:2, /* SIB byte */
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index:4,
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base:4;
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uint8_t disp_bytes;
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uint8_t imm_bytes;
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uint8_t scale;
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enum cpu_reg_name base_register; /* CPU_REG_xyz */
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enum cpu_reg_name index_register; /* CPU_REG_xyz */
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enum cpu_reg_name segment_register; /* CPU_REG_xyz */
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int64_t displacement; /* optional addr displacement */
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int64_t immediate; /* optional immediate operand */
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uint8_t decoded; /* set to 1 if successfully decoded */
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struct instr_emul_vie_op op; /* opcode description */
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};
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#define PSL_C 0x00000001U /* carry bit */
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#define PSL_PF 0x00000004U /* parity bit */
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#define PSL_AF 0x00000010U /* bcd carry bit */
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#define PSL_Z 0x00000040U /* zero bit */
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#define PSL_N 0x00000080U /* negative bit */
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#define PSL_T 0x00000100U /* trace enable bit */
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#define PSL_I 0x00000200U /* interrupt enable bit */
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#define PSL_D 0x00000400U /* string instruction direction bit */
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#define PSL_V 0x00000800U /* overflow bit */
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#define PSL_IOPL 0x00003000U /* i/o privilege level */
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#define PSL_NT 0x00004000U /* nested task bit */
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#define PSL_RF 0x00010000U /* resume flag bit */
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#define PSL_VM 0x00020000U /* virtual 8086 mode bit */
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#define PSL_AC 0x00040000U /* alignment checking */
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#define PSL_VIF 0x00080000U /* virtual interrupt enable */
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#define PSL_VIP 0x00100000U /* virtual interrupt pending */
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#define PSL_ID 0x00200000U /* identification bit */
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/*
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* The 'access' field has the format specified in Table 21-2 of the Intel
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* Architecture Manual vol 3b.
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*
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* XXX The contents of the 'access' field are architecturally defined except
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* bit 16 - Segment Unusable.
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*/
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struct seg_desc {
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uint64_t base;
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uint32_t limit;
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uint32_t access;
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};
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/*
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* Protections are chosen from these bits, or-ed together
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*/
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#define PROT_NONE 0x00U /* no permissions */
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#define PROT_READ 0x01U /* pages can be read */
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#define PROT_WRITE 0x02U /* pages can be written */
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#define PROT_EXEC 0x04U /* pages can be executed */
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#define SEG_DESC_TYPE(access) ((access) & 0x001fU)
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#define SEG_DESC_DPL(access) (((access) >> 5) & 0x3U)
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#define SEG_DESC_PRESENT(access) (((access) & 0x0080U) != 0U)
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#define SEG_DESC_DEF32(access) (((access) & 0x4000U) != 0U)
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#define SEG_DESC_GRANULARITY(access) (((access) & 0x8000U) != 0U)
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#define SEG_DESC_UNUSABLE(access) (((access) & 0x10000U) != 0U)
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struct vm_guest_paging {
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uint64_t cr3;
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uint8_t cpl;
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enum vm_cpu_mode cpu_mode;
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enum vm_paging_mode paging_mode;
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};
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struct instr_emul_ctxt {
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struct instr_emul_vie vie;
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struct vm_guest_paging paging;
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struct vcpu *vcpu;
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};
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int vm_get_register(struct vcpu *vcpu, enum cpu_reg_name reg, uint64_t *retval);
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int vm_set_register(struct vcpu *vcpu, enum cpu_reg_name reg, uint64_t val);
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int vm_get_seg_desc(struct vcpu *vcpu, enum cpu_reg_name reg,
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struct seg_desc *ret_desc);
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int vm_set_seg_desc(struct vcpu *vcpu, enum cpu_reg_name reg,
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struct seg_desc *desc);
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#endif
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