mirror of
https://github.com/projectacrn/acrn-hypervisor.git
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4dc39fdb8e
There are some integer type conversions reported by static analysis tool for vcpu id, number of created vcpus, and vpid, to reduce these type conversions, redesign vcpu id, number of created vcpus, and vpid type as uint16_t as per their usage, related 16-bit atomic operations shall be added in HV. MISRA C requires that all unsigned constants should have the suffix 'U' (e.g. 0xffU), but the assembler may not accept such C-style constants. Add 16-bit atomic add/dec/store operations; Update temporary variables type and parameters type of related caller; Update vpid type as uint16_t; Replace Macro with constant value for CPU_PAGE_SIZE. Note: According to SDM A.10, there are some bits defined in the IA32_VMX_EPT_VPID_CAP MSR to support the INVVPID instruction, these bits don't mean actual VPID, so the vpid field in the data struct vmx_capability doesn't be updated. V1--V2: update comments for assembly code as per coding style; Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
242 lines
6.6 KiB
ArmAsm
242 lines
6.6 KiB
ArmAsm
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <cpu.h>
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#include <mmu.h>
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#include <gdt.h>
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#include <idt.h>
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#include <msr.h>
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/* NOTE:
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*
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* MISRA C requires that all unsigned constants should have the suffix 'U'
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* (e.g. 0xffU), but the assembler may not accept such C-style constants. For
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* example, binutils 2.26 fails to compile assembly in that case. To work this
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* around, all unsigned constants must be explicitly spells out in assembly
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* with a comment tracking the original expression from which the magic
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* number is calculated. As an example:
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*
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* /* 0x00000668 =
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* * (CR4_DE | CR4_PAE | CR4_MCE | CR4_OSFXSR | CR4_OSXMMEXCPT) *\/
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* movl $0x00000668, %eax
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*
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* Make sure that these numbers are updated accordingly if the definition of
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* the macros involved are changed.
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*/
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/* MULTIBOOT HEADER */
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#define MULTIBOOT_HEADER_MAGIC 0x1badb002
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#define MULTIBOOT_HEADER_FLAGS 0x00000002 /*flags bit 1 : enable mem_*, mmap_**/
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.section multiboot_header, "a"
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.align 4
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/* header magic */
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.long MULTIBOOT_HEADER_MAGIC
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/* header flags - flags bit 6 : enable mmap_* */
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.long MULTIBOOT_HEADER_FLAGS
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/* header checksum = -(magic + flags) */
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.long -(MULTIBOOT_HEADER_MAGIC + MULTIBOOT_HEADER_FLAGS)
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.section entry, "ax"
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.align 8
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.code32
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.global cpu_primary_start_32
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cpu_primary_start_32:
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/* Disable interrupts */
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cli
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/* Clear direction flag */
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cld
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/* save eax and ebx */
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movl %eax, %esp
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movl %ebx, %ebp
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/* detect whether it is in long mode
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*
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* 0xc0000080 = MSR_IA32_EFER
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*/
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movl $0xc0000080, %ecx
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rdmsr
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/* 0x400 = MSR_IA32_EFER_LMA_BIT */
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test $0x400, %eax
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/* jump to 64bit entry if it is already in long mode */
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jne cpu_primary_start_64
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/* save the MULTBOOT magic number & MBI */
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movl %esp, (boot_regs)
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movl %ebp, (boot_regs+4)
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/* Disable paging */
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mov %cr0, %ebx
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/* 0x7fffffff = ~CR0_PG */
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andl $0x7fffffff, %ebx
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mov %ebx, %cr0
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/* Set DE, PAE, MCE and OS support bits in CR4
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* 0x00000668 =
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* (CR4_DE | CR4_PAE | CR4_MCE | CR4_OSFXSR | CR4_OSXMMEXCPT) */
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movl $0x00000668, %eax
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mov %eax, %cr4
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/* Set CR3 to PML4 table address */
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movl $cpu_boot32_page_tables_start, %edi
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mov %edi, %cr3
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/* Set LME bit in EFER */
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/* 0xc0000080 = MSR_IA32_EFER */
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movl $0xc0000080, %ecx
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rdmsr
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/* 0x00000100 = MSR_IA32_EFER_LME_BIT */
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orl $0x00000100, %eax
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wrmsr
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/* Enable paging, protection, numeric error and co-processor
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monitoring in CR0 to enter long mode */
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mov %cr0, %ebx
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/* 0x80000023 = (CR0_PG | CR0_PE | CR0_MP | CR0_NE) */
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orl $0x80000023, %ebx
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mov %ebx, %cr0
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/* Load temportary GDT pointer value */
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mov $cpu_primary32_gdt_ptr, %ebx
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lgdt (%ebx)
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/* Perform a long jump based to start executing in 64-bit mode */
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ljmp $HOST_GDT_RING0_CODE_SEL, $primary_start_long_mode
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.code64
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.org 0x200
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.global cpu_primary_start_64
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cpu_primary_start_64:
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/* save the MULTBOOT magic number & MBI */
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lea boot_regs(%rip), %rax
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movl %edi, (%rax)
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movl %esi, 4(%rax)
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primary_start_long_mode:
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/* Initialize temporary stack pointer */
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lea _ld_bss_end(%rip), %rsp
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/*0x1000 = CPU_PAGE_SIZE*/
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add $0x1000,%rsp
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/* 16 = CPU_STACK_ALIGN */
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and $(~(16 - 1)),%rsp
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/*
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* Fix up the .rela sections
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* Notes: this includes the fixup to IDT tables and temporary
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* page tables
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*/
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call _relocate
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/* Load temportary GDT pointer value */
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lea cpu_primary32_gdt_ptr(%rip), %rbx
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lgdt (%ebx)
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/* Set the correct long jump address */
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lea jmpbuf(%rip), %rax
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lea after(%rip), %rbx
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mov %rbx, (%rax)
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rex.w ljmp *(%rax)
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.data
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jmpbuf: .quad 0
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.word HOST_GDT_RING0_CODE_SEL
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.text
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after:
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// load all selector registers with appropriate values
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xor %edx, %edx
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lldt %dx
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movl $HOST_GDT_RING0_DATA_SEL,%eax
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mov %eax,%ss // Was 32bit POC Stack
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mov %eax,%ds // Was 32bit POC Data
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mov %eax,%es // Was 32bit POC Data
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mov %edx,%fs // Was 32bit POC Data
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mov %edx,%gs // Was 32bit POC CLS
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/*
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* Fix up the IDT desciptors
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* The relocation delta in IDT tables has been fixed in _relocate()
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*/
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leal HOST_IDT(%rip), %edx
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movl $HOST_IDT_ENTRIES, %ecx
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.fixup_idt_entries:
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xorl %eax, %eax
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xchgl %eax, 12(%edx) /* Set rsvd bits to 0; eax now has
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high 32 of entry point */
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xchgl %eax, 8(%edx) /* Set bits 63..32 of entry point;
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eax now has low 32 of entry point */
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movw %ax, (%edx) /* Set bits 0-15 of procedure entry
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point */
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shr $16, %eax
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movw %ax, 6(%edx) /* Set bits 16-31 of entry point */
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addl $X64_IDT_DESC_SIZE,%edx
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loop .fixup_idt_entries
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/* Load IDT */
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lea HOST_IDTR(%rip), %rbx
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lidtq (%rbx)
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/* continue with chipset level initialization */
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call bsp_boot_init
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loop:
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jmp loop
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.align 4
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.global boot_regs
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boot_regs:
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.long 0x00000000
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.long 0x00000000
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/* GDT table */
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.align 4
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cpu_primary32_gdt:
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.quad 0x0000000000000000
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.quad 0x00af9b000000ffff
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.quad 0x00cf93000000ffff
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cpu_primary32_gdt_end:
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/* GDT pointer */
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.align 2
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cpu_primary32_gdt_ptr:
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.short (cpu_primary32_gdt_end - cpu_primary32_gdt) - 1
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.quad cpu_primary32_gdt
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/* PML4, PDPT, and PD tables initialized to map first 4 GBytes of memory */
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/*0x1000 = CPU_PAGE_SIZE*/
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.align 0x1000
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.global cpu_boot32_page_tables_start
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cpu_boot32_page_tables_start:
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/* 0x3 = (IA32E_COMM_P_BIT | IA32E_COMM_RW_BIT) */
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.quad cpu_primary32_pdpt_addr + 0x3
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/*0x1000 = CPU_PAGE_SIZE*/
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.align 0x1000
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cpu_primary32_pdpt_addr:
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address = 0
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.rept 4
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/* 0x3 = (IA32E_COMM_P_BIT | IA32E_COMM_RW_BIT) */
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.quad cpu_primary32_pdt_addr + address + 0x3
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/*0x1000 = CPU_PAGE_SIZE*/
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address = address + 0x1000
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.endr
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/*0x1000 = CPU_PAGE_SIZE*/
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.align 0x1000
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cpu_primary32_pdt_addr:
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address = 0
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.rept 2048
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/* 0x83 = (IA32E_PDPTE_PS_BIT | IA32E_COMM_P_BIT | IA32E_COMM_RW_BIT) */
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.quad address + 0x83
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address = address + 0x200000
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.endr
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