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bd0e83fa5f
Follow multi-arch, add risc-v MMIO APIs with memory order, without PIO support. Tracked-On: #8807 Signed-off-by: Haicheng Li <haicheng.li@linux.intel.com> Co-developed-by: Fei Li <fei1.li@intel.com> Signed-off-by: Fei Li <fei1.li@intel.com> Signed-off-by: Haoyu Tang <haoyu.tang@intel.com> Reviewed-by: Yifan Liu <yifan1.liu@intel.com>
127 lines
2.8 KiB
C
127 lines
2.8 KiB
C
/*
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* Copyright (C) 2023-2025 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Authors:
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* Haicheng Li <haicheng.li@intel.com>
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*/
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#ifndef RISCV_IO_H
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#define RISCV_IO_H
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#include <barrier.h>
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#define HAS_ARCH_MMIO
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/*
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* Generic I/O memory access primitives.
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*/
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static inline void writeb(uint8_t val, volatile void *addr)
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{
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asm volatile("sb %0, 0(%1)" : : "r" (val), "r" (addr) : "memory");
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}
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static inline void writew(uint16_t val, volatile void *addr)
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{
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asm volatile("sh %w0, 0(%1)" : : "r" (val), "r" (addr) : "memory");
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}
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static inline void writel(uint32_t val, volatile void *addr)
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{
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asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr) : "memory");
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}
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static inline void writeq(uint64_t val, volatile void *addr)
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{
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asm volatile("sd %0, 0(%1)" : : "r" (val), "r" (addr) : "memory");
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}
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static inline uint8_t readb(const volatile void *addr)
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{
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uint8_t val;
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asm volatile("lb %0, 0(%1)": "=r" (val) : "r" (addr) : "memory");
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return val;
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}
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static inline uint16_t readw(const volatile void *addr)
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{
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uint16_t val;
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asm volatile("lh %0, 0(%1)": "=r" (val) : "r" (addr) : "memory");
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return val;
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}
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static inline uint32_t readl(const volatile void *addr)
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{
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uint32_t val;
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asm volatile("lw %0, 0(%1)": "=r" (val) : "r" (addr) : "memory");
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return val;
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}
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static inline uint64_t readq(const volatile void *addr)
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{
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uint64_t val;
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asm volatile("ld %0, 0(%1)": "=r" (val) : "r" (addr) : "memory");
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return val;
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}
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/*
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* Strictly ordered I/O memory access primitives.
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*/
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static inline uint8_t arch_mmio_read8(const volatile void *addr)
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{
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uint8_t val = readb(addr);
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cpu_read_memory_barrier();
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return val;
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}
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static inline uint16_t arch_mmio_read16(const volatile void *addr)
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{
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uint16_t val = readw(addr);
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cpu_read_memory_barrier();
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return val;
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}
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static inline uint32_t arch_mmio_read32(const volatile void *addr)
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{
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uint32_t val = readl(addr);
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cpu_read_memory_barrier();
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return val;
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}
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static inline uint64_t arch_mmio_read64(const volatile void *addr)
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{
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uint64_t val = readq(addr);
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cpu_read_memory_barrier();
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return val;
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}
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static inline void arch_mmio_write8(uint8_t val, volatile void *addr)
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{
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cpu_write_memory_barrier();
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writeb(val, addr);
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}
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static inline void arch_mmio_write16(uint16_t val, volatile void *addr)
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{
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cpu_write_memory_barrier();
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writew(val, addr);
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}
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static inline void arch_mmio_write32(uint32_t val, volatile void *addr)
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{
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cpu_write_memory_barrier();
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writel(val, addr);
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}
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static inline void arch_mmio_write64(uint64_t val, volatile void *addr)
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{
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cpu_write_memory_barrier();
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writeq(val, addr);
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}
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#endif /* RISCV_IO_H */
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