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47944d975d
Follow multi-arch design, implement the mandatory arch atomic functions declared in common atomic.h for risc-v support. Tracked-On: #8803 Signed-off-by: Haicheng Li <haicheng.li@linux.intel.com> Co-developed-by: Haoyu Tang <haoyu.tang@intel.com> Signed-off-by: Haoyu Tang <haoyu.tang@intel.com> Reviewed-by: Yifan Liu <yifan1.liu@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>
118 lines
3.2 KiB
C
118 lines
3.2 KiB
C
/*
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* Copyright (C) 2023-2025 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Authors:
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* Haicheng Li <haicheng.li@intel.com>
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* Haoyu Tang <haoyu.tang@intel.com>
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*/
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#ifndef RISCV_LIB_ATOMIC_H
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#define RISCV_LIB_ATOMIC_H
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#define build_atomic_inc(name, type, size) \
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static inline void arch_atomic_##name(type *ptr) \
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{ \
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type inc = 1; \
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asm volatile("amoadd." size " zero, %1, %0" \
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: "+A" (*ptr) \
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: "r" (inc) \
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: "memory"); \
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}
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build_atomic_inc(inc32, uint32_t, "w")
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build_atomic_inc(inc64, uint64_t, "d")
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#define build_atomic_dec(name, type, size) \
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static inline void arch_atomic_##name(type *ptr) \
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{ \
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type dec = -1; \
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asm volatile("amoadd." size " zero, %1, %0" \
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: "+A" (*ptr) \
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: "r" (dec) \
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: "memory"); \
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}
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build_atomic_dec(dec32, uint32_t, "w")
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build_atomic_dec(dec64, uint64_t, "d")
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#define build_atomic_swap(name, type, size) \
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static inline type arch_atomic_##name(type *ptr, type v) \
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{ \
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asm volatile("amoswap." size " %0, %2, %1" \
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: "=r" (v), "+A" (*ptr) \
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: "r" (v) \
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: "memory"); \
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return v; \
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}
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build_atomic_swap(swap32, uint32_t, "w")
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build_atomic_swap(swap64, uint64_t, "d")
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#define build_atomic_op(name, size, type, op) \
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static inline type arch_atomic_##name##_return(type *v, type i) \
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{ \
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type ret; \
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asm volatile("amoadd." size ".aqrl %1, %2, %0\n\t" \
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: "+A"(*v), "=r"(ret) \
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: "r"(op i) \
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: "memory"); \
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return ret op i; \
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}
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build_atomic_op(add, "w", int32_t, +)
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build_atomic_op(add64, "d", int64_t, +)
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build_atomic_op(sub, "w", int32_t, -)
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build_atomic_op(sub64, "d", int64_t, -)
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static inline int32_t arch_atomic_inc_return(int32_t *v)
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{
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return arch_atomic_add_return(v, 1);
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}
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static inline int32_t arch_atomic_dec_return(int32_t *v)
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{
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return arch_atomic_sub_return(v, 1);
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}
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static inline int64_t arch_atomic_inc64_return(int64_t *v)
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{
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return arch_atomic_add64_return(v, 1);
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}
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static inline int64_t arch_atomic_dec64_return(int64_t *v)
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{
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return arch_atomic_sub64_return(v, 1);
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}
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#ifdef RISCV_ISA_EXT_ZACAS /* extension `zacas' is required */
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#define build_cmpxchg(name, size, type) \
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static inline type arch_atomic_##name(volatile type *ptr, type old, type new) \
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{ \
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type ret; \
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ret = old; \
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asm volatile("amocas." size ".aqrl %0, %z2, %1\n" \
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: "+&r"(ret), "+A"(*ptr) \
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: "rJ"(new) \
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: "memory"); \
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return ret; \
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}
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#else /* RISCV_ISA_EXT_ZACAS not defined */
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#define build_cmpxchg(name, size, type) \
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static inline type arch_atomic_##name(volatile type *ptr, type old, type new) \
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{ \
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type ret; \
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register type rc; \
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asm volatile("0: lr." size " %0, %2\n" \
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" bne %0, %z3, 1f\n" \
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" sc." size ".rl %1, %z4, %2\n" \
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" bnez %1, 0b\n" \
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" fence rw, rw\n" \
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"1:\n" \
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: "=&r"(ret), "=&r"(rc), "+A"(*ptr) \
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: "rJ"(old), "rJ"(new) \
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: "memory"); \
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return ret; \
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}
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#endif /* RISCV_ISA_EXT_ZACAS */
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build_cmpxchg(cmpxchg32, "w", uint32_t)
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build_cmpxchg(cmpxchg64, "d", uint64_t)
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#endif /* RISCV_LIB_ATOMIC_H */ |