Qian Wang a557105e71 hv: ept: set EPT cache attribute to WB for pSRAM ...

pSRAM memory should be cachable. However, it's not a RAM or a normal MMIO,
so we can't use the an exist API to do the EPT mapping and set the EPT cache
attribute to WB for it. Now we assume that SOS must assign the PSRAM area as
a whole and as a separate memory region whose base address is PSRAM_BASE_HPA.
If the hpa of the EPT mapping region is equal to PSRAM_BASE_HPA, we think this
EPT mapping is for pSRAM, we change the EPT mapping cache attribute to WB.

And fix a minor bug when SOS trap out to emulate wbinvd when pSRAM is enabled.

Tracked-On: #5330
Signed-off-by: Qian Wang <qian1.wang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>

2020-11-02 15:56:30 +08:00

..

event.c

hv: reset vcpu events in reset_vcpu

2020-02-23 16:27:57 +08:00

hv_main.c

hv:add per-vm lock for vm & vcpu state change

2020-07-20 11:22:17 +08:00

hypercall.c

hv: ept: set EPT cache attribute to WB for pSRAM

2020-11-02 15:56:30 +08:00

ptdev.c

hv:unify spin_lock initialization

2020-07-02 09:40:29 +08:00

sched_bvt.c

hv: list: rename list_entry to container_of

2020-03-31 10:57:47 +08:00

sched_iorr.c

hv: sched_iorr: add some interfaces implementation of sched_iorr

2019-12-11 09:31:39 +08:00

sched_noop.c

hv: sched: decouple scheduler from schedule framework

2019-10-25 13:00:21 +08:00

schedule.c

hv: Fix thread status mess if wake_thread() happens in transition stage

2020-08-20 10:32:31 +08:00

softirq.c

softirq: move softirq from hv_main to interrupt context

2019-07-22 09:55:06 +08:00

trusty_hypercall.c

hv: rename the ACRN_DBG_XXX

2020-01-14 10:21:23 +08:00

vm_load.c

hv: remove de-privilege boot mode support and remove vboot wrappers

2020-10-21 15:09:26 +08:00