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a557105e71
pSRAM memory should be cachable. However, it's not a RAM or a normal MMIO, so we can't use the an exist API to do the EPT mapping and set the EPT cache attribute to WB for it. Now we assume that SOS must assign the PSRAM area as a whole and as a separate memory region whose base address is PSRAM_BASE_HPA. If the hpa of the EPT mapping region is equal to PSRAM_BASE_HPA, we think this EPT mapping is for pSRAM, we change the EPT mapping cache attribute to WB. And fix a minor bug when SOS trap out to emulate wbinvd when pSRAM is enabled. Tracked-On: #5330 Signed-off-by: Qian Wang <qian1.wang@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
ACRN Hypervisor ############### The open source `Project ACRN`_ defines a device hypervisor reference stack and an architecture for running multiple software subsystems, managed securely, on a consolidated system by means of a virtual machine manager. It also defines a reference framework implementation for virtual device emulation, called the "ACRN Device Model". The ACRN Hypervisor is a Type 1 reference hypervisor stack, running directly on the bare-metal hardware, and is suitable for a variety of IoT and embedded device solutions. The ACRN hypervisor addresses the gap that currently exists between datacenter hypervisors, and hard partitioning hypervisors. The ACRN hypervisor architecture partitions the system into different functional domains, with carefully selected guest OS sharing optimizations for IoT and embedded devices. You can find out more about Project ACRN on the `Project ACRN documentation`_ website. .. _`Project ACRN`: https://projectacrn.org .. _`ACRN Hypervisor`: https://github.com/projectacrn/acrn-hypervisor .. _`Project ACRN documentation`: https://projectacrn.github.io/