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b4f1e5aa85
Due to the fact that i915 iommu doesn't support snoop, hence it can't access memory when the SNOOP bit of Secondary Level page PTE (SL-PTE) is set, this will cause many undefined issues such as invisible cursor in WaaG etc. Current hv design uses EPT as Scondary Leval Page for iommu, and this patch removes the codes of setting SNOOP bit in both EPT-PTE and SL-PTE to avoid errors. And according to SDM 28.2.2, the SNOOP bit (11th bit) will be ignored by EPT, so it will not affect the CPU address translation. Tracked-On: #4509 Signed-off-by: Xiaoguang Wu <xiaoguang.wu@intel.com> Reviewed-by: Binbin Wu <binbin.wu@intel.com> Acked-by: Eddie Dong <eddie.dong@Intel.com>
ACRN Hypervisor ############### The open source `Project ACRN`_ defines a device hypervisor reference stack and an architecture for running multiple software subsystems, managed securely, on a consolidated system by means of a virtual machine manager. It also defines a reference framework implementation for virtual device emulation, called the "ACRN Device Model". The ACRN Hypervisor is a Type 1 reference hypervisor stack, running directly on the bare-metal hardware, and is suitable for a variety of IoT and embedded device solutions. The ACRN hypervisor addresses the gap that currently exists between datacenter hypervisors, and hard partitioning hypervisors. The ACRN hypervisor architecture partitions the system into different functional domains, with carefully selected guest OS sharing optimizations for IoT and embedded devices. You can find out more about Project ACRN on the `Project ACRN documentation`_ website. .. _`Project ACRN`: https://projectacrn.org .. _`ACRN Hypervisor`: https://github.com/projectacrn/acrn-hypervisor .. _`Project ACRN documentation`: https://projectacrn.github.io/