mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-05-03 22:17:03 +00:00
8b94957774
Misra C required signed/unsigned conversion with cast. V1->V2: a.split patch to patch series V2->V3: a.change the uint64_t type numeric constant's suffix from U to UL Signed-off-by: Huihuang Shi <huihuang.shi@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
343 lines
7.5 KiB
C
343 lines
7.5 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <hypervisor.h>
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#include "instr_emul_wrapper.h"
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#include "instr_emul.h"
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static int
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encode_vmcs_seg_desc(int seg, uint32_t *base, uint32_t *lim, uint32_t *acc);
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static int32_t
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get_vmcs_field(int ident);
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static bool
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is_segment_register(int reg);
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static bool
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is_descriptor_table(int reg);
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int vm_get_register(struct vcpu *vcpu, int reg, uint64_t *retval)
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{
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struct run_context *cur_context;
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if (vcpu == NULL)
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return -EINVAL;
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if ((reg >= VM_REG_LAST) || (reg < VM_REG_GUEST_RAX))
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return -EINVAL;
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if ((reg >= VM_REG_GUEST_RAX) && (reg <= VM_REG_GUEST_RDI)) {
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cur_context =
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&vcpu->arch_vcpu.contexts[vcpu->arch_vcpu.cur_context];
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*retval = cur_context->guest_cpu_regs.longs[reg];
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} else if ((reg > VM_REG_GUEST_RDI) && (reg < VM_REG_LAST)) {
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int32_t field = get_vmcs_field(reg);
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if (field != -1)
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*retval = exec_vmread(field);
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else
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return -EINVAL;
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}
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return 0;
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}
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int vm_set_register(struct vcpu *vcpu, int reg, uint64_t val)
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{
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struct run_context *cur_context;
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if (vcpu == NULL)
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return -EINVAL;
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if ((reg >= VM_REG_LAST) || (reg < VM_REG_GUEST_RAX))
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return -EINVAL;
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if ((reg >= VM_REG_GUEST_RAX) && (reg <= VM_REG_GUEST_RDI)) {
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cur_context =
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&vcpu->arch_vcpu.contexts[vcpu->arch_vcpu.cur_context];
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cur_context->guest_cpu_regs.longs[reg] = val;
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} else if ((reg > VM_REG_GUEST_RDI) && (reg < VM_REG_LAST)) {
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int32_t field = get_vmcs_field(reg);
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if (field != -1)
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exec_vmwrite(field, val);
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else
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return -EINVAL;
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}
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return 0;
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}
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int vm_set_seg_desc(struct vcpu *vcpu, int seg, struct seg_desc *ret_desc)
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{
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int error;
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uint32_t base, limit, access;
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if ((vcpu == NULL) || (ret_desc == NULL))
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return -EINVAL;
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if (!is_segment_register(seg) && !is_descriptor_table(seg))
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return -EINVAL;
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error = encode_vmcs_seg_desc(seg, &base, &limit, &access);
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if ((error != 0) || (access == 0xffffffff))
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return -EINVAL;
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exec_vmwrite(base, ret_desc->base);
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exec_vmwrite(limit, ret_desc->limit);
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exec_vmwrite(access, ret_desc->access);
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return 0;
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}
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int vm_get_seg_desc(struct vcpu *vcpu, int seg, struct seg_desc *desc)
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{
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int error;
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uint32_t base, limit, access;
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if ((vcpu == NULL) || (desc == NULL))
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return -EINVAL;
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if (!is_segment_register(seg) && !is_descriptor_table(seg))
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return -EINVAL;
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error = encode_vmcs_seg_desc(seg, &base, &limit, &access);
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if ((error != 0) || (access == 0xffffffff))
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return -EINVAL;
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desc->base = exec_vmread(base);
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desc->limit = exec_vmread(limit);
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desc->access = exec_vmread(access);
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return 0;
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}
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static bool is_descriptor_table(int reg)
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{
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switch (reg) {
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case VM_REG_GUEST_IDTR:
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case VM_REG_GUEST_GDTR:
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return true;
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default:
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return false;
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}
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}
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static bool is_segment_register(int reg)
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{
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switch (reg) {
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case VM_REG_GUEST_ES:
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case VM_REG_GUEST_CS:
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case VM_REG_GUEST_SS:
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case VM_REG_GUEST_DS:
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case VM_REG_GUEST_FS:
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case VM_REG_GUEST_GS:
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case VM_REG_GUEST_TR:
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case VM_REG_GUEST_LDTR:
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return true;
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default:
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return false;
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}
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}
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static int encode_vmcs_seg_desc(int seg, uint32_t *base, uint32_t *lim,
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uint32_t *acc)
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{
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switch (seg) {
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case VM_REG_GUEST_ES:
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*base = VMX_GUEST_ES_BASE;
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*lim = VMX_GUEST_ES_LIMIT;
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*acc = VMX_GUEST_ES_ATTR;
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break;
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case VM_REG_GUEST_CS:
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*base = VMX_GUEST_CS_BASE;
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*lim = VMX_GUEST_CS_LIMIT;
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*acc = VMX_GUEST_CS_ATTR;
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break;
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case VM_REG_GUEST_SS:
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*base = VMX_GUEST_SS_BASE;
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*lim = VMX_GUEST_SS_LIMIT;
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*acc = VMX_GUEST_SS_ATTR;
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break;
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case VM_REG_GUEST_DS:
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*base = VMX_GUEST_DS_BASE;
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*lim = VMX_GUEST_DS_LIMIT;
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*acc = VMX_GUEST_DS_ATTR;
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break;
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case VM_REG_GUEST_FS:
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*base = VMX_GUEST_FS_BASE;
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*lim = VMX_GUEST_FS_LIMIT;
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*acc = VMX_GUEST_FS_ATTR;
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break;
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case VM_REG_GUEST_GS:
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*base = VMX_GUEST_GS_BASE;
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*lim = VMX_GUEST_GS_LIMIT;
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*acc = VMX_GUEST_GS_ATTR;
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break;
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case VM_REG_GUEST_TR:
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*base = VMX_GUEST_TR_BASE;
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*lim = VMX_GUEST_TR_LIMIT;
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*acc = VMX_GUEST_TR_ATTR;
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break;
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case VM_REG_GUEST_LDTR:
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*base = VMX_GUEST_LDTR_BASE;
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*lim = VMX_GUEST_LDTR_LIMIT;
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*acc = VMX_GUEST_LDTR_ATTR;
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break;
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case VM_REG_GUEST_IDTR:
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*base = VMX_GUEST_IDTR_BASE;
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*lim = VMX_GUEST_IDTR_LIMIT;
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*acc = 0xffffffffU;
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break;
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case VM_REG_GUEST_GDTR:
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*base = VMX_GUEST_GDTR_BASE;
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*lim = VMX_GUEST_GDTR_LIMIT;
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*acc = 0xffffffffU;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int32_t get_vmcs_field(int ident)
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{
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switch (ident) {
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case VM_REG_GUEST_CR0:
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return VMX_GUEST_CR0;
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case VM_REG_GUEST_CR3:
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return VMX_GUEST_CR3;
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case VM_REG_GUEST_CR4:
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return VMX_GUEST_CR4;
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case VM_REG_GUEST_DR7:
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return VMX_GUEST_DR7;
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case VM_REG_GUEST_RSP:
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return VMX_GUEST_RSP;
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case VM_REG_GUEST_RIP:
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return VMX_GUEST_RIP;
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case VM_REG_GUEST_RFLAGS:
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return VMX_GUEST_RFLAGS;
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case VM_REG_GUEST_ES:
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return VMX_GUEST_ES_SEL;
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case VM_REG_GUEST_CS:
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return VMX_GUEST_CS_SEL;
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case VM_REG_GUEST_SS:
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return VMX_GUEST_SS_SEL;
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case VM_REG_GUEST_DS:
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return VMX_GUEST_DS_SEL;
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case VM_REG_GUEST_FS:
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return VMX_GUEST_FS_SEL;
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case VM_REG_GUEST_GS:
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return VMX_GUEST_GS_SEL;
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case VM_REG_GUEST_TR:
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return VMX_GUEST_TR_SEL;
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case VM_REG_GUEST_LDTR:
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return VMX_GUEST_LDTR_SEL;
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case VM_REG_GUEST_EFER:
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return VMX_GUEST_IA32_EFER_FULL;
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case VM_REG_GUEST_PDPTE0:
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return VMX_GUEST_PDPTE0_FULL;
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case VM_REG_GUEST_PDPTE1:
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return VMX_GUEST_PDPTE1_FULL;
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case VM_REG_GUEST_PDPTE2:
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return VMX_GUEST_PDPTE2_FULL;
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case VM_REG_GUEST_PDPTE3:
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return VMX_GUEST_PDPTE3_FULL;
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default:
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return -1;
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}
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}
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static void get_guest_paging_info(struct vcpu *vcpu, struct emul_cnx *emul_cnx,
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uint32_t csar)
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{
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uint32_t cpl;
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ASSERT(emul_cnx != NULL && vcpu != NULL, "Error in input arguments");
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cpl = (csar >> 5) & 3U;
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emul_cnx->paging.cr3 =
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vcpu->arch_vcpu.contexts[vcpu->arch_vcpu.cur_context].cr3;
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emul_cnx->paging.cpl = cpl;
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emul_cnx->paging.cpu_mode = get_vcpu_mode(vcpu);
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emul_cnx->paging.paging_mode = get_vcpu_paging_mode(vcpu);
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}
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static int mmio_read(struct vcpu *vcpu, __unused uint64_t gpa, uint64_t *rval,
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__unused int size, __unused void *arg)
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{
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if (vcpu == NULL)
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return -EINVAL;
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*rval = vcpu->mmio.value;
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return 0;
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}
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static int mmio_write(struct vcpu *vcpu, __unused uint64_t gpa, uint64_t wval,
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__unused int size, __unused void *arg)
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{
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if (vcpu == NULL)
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return -EINVAL;
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vcpu->mmio.value = wval;
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return 0;
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}
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int decode_instruction(struct vcpu *vcpu)
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{
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struct emul_cnx *emul_cnx;
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uint32_t csar;
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int retval = 0;
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enum vm_cpu_mode cpu_mode;
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emul_cnx = &per_cpu(g_inst_ctxt, vcpu->pcpu_id);
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emul_cnx->vcpu = vcpu;
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retval = vie_init(&emul_cnx->vie, vcpu);
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if (retval < 0) {
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if (retval != -EFAULT) {
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pr_err("decode instruction failed @ 0x%016llx:",
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vcpu->arch_vcpu.
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contexts[vcpu->arch_vcpu.cur_context].rip);
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}
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return retval;
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}
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csar = exec_vmread(VMX_GUEST_CS_ATTR);
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get_guest_paging_info(vcpu, emul_cnx, csar);
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cpu_mode = get_vcpu_mode(vcpu);
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retval = __decode_instruction(cpu_mode, SEG_DESC_DEF32(csar),
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&emul_cnx->vie);
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if (retval != 0) {
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pr_err("decode instruction failed @ 0x%016llx:",
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vcpu->arch_vcpu.contexts[vcpu->arch_vcpu.cur_context].rip);
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return -EINVAL;
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}
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return emul_cnx->vie.opsize;
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}
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int emulate_instruction(struct vcpu *vcpu)
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{
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struct emul_cnx *emul_cnx;
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struct vm_guest_paging *paging;
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int retval = 0;
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uint64_t gpa = vcpu->mmio.paddr;
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mem_region_read_t mread = mmio_read;
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mem_region_write_t mwrite = mmio_write;
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emul_cnx = &per_cpu(g_inst_ctxt, vcpu->pcpu_id);
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paging = &emul_cnx->paging;
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retval = vmm_emulate_instruction(vcpu, gpa,
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&emul_cnx->vie, paging, mread, mwrite, NULL);
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return retval;
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}
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