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https://github.com/projectacrn/acrn-hypervisor.git
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b8a021d658
Upcoming intel platforms can support both L2 and L3 but our current code only supports either L2 or L3 CAT. So split the MSRs so that we can support allocation for both L2 and L3. This patch does the following, 1. splits programming of L2 and L3 cache resource based on the resource ID. 2. Replace generic platform_clos_array struct with resource specific struct in all the existing board.c files. Tracked-On: #3715 Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
99 lines
2.6 KiB
C
99 lines
2.6 KiB
C
/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <types.h>
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#include <cpu.h>
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#include <cpu_caps.h>
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#include <cpufeatures.h>
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#include <cpuid.h>
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#include <errno.h>
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#include <logmsg.h>
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#include <rdt.h>
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#include <board.h>
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#include <vm_config.h>
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#include <msr.h>
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struct cat_hw_info cat_cap_info;
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const uint16_t hv_clos = 0U;
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static uint16_t platform_clos_num = MAX_PLATFORM_CLOS_NUM;
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int32_t init_cat_cap_info(void)
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{
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uint32_t eax = 0U, ebx = 0U, ecx = 0U, edx = 0U;
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int32_t ret = 0;
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if (pcpu_has_cap(X86_FEATURE_CAT)) {
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cpuid_subleaf(CPUID_RSD_ALLOCATION, 0, &eax, &ebx, &ecx, &edx);
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/* If support L3 CAT, EBX[1] is set */
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if ((ebx & 2U) != 0U) {
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cat_cap_info.res_id = CAT_RESID_L3;
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}
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/* If support L2 CAT, EBX[2] is set */
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if ((ebx & 4U) != 0U) {
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cat_cap_info.res_id = CAT_RESID_L2;
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}
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cat_cap_info.enabled = true;
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/* CPUID.(EAX=0x10,ECX=ResID):EAX[4:0] reports the length of CBM supported
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* CPUID.(EAX=0x10,ECX=ResID):EBX[31:0] indicates the corresponding uints
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* may be used by other entities such as graphic and H/W outside processor.
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* CPUID.(EAX=0x10,ECX=ResID):EDX[15:0] reports the maximun CLOS supported
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*/
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cpuid_subleaf(CPUID_RSD_ALLOCATION, cat_cap_info.res_id, &eax, &ebx, &ecx, &edx);
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cat_cap_info.cbm_len = (uint16_t)((eax & 0x1fU) + 1U);
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cat_cap_info.bitmask = ebx;
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cat_cap_info.clos_max = (uint16_t)(edx & 0xffffU);
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if ((platform_clos_num != 0U) && ((cat_cap_info.clos_max + 1U) != platform_clos_num)) {
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pr_err("%s clos_max:%hu, platform_clos_num:%u\n", __func__, cat_cap_info.clos_max, platform_clos_num);
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ret = -EINVAL;
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}
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}
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return ret;
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}
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void setup_clos(uint16_t pcpu_id)
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{
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uint16_t i;
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uint32_t msr_index;
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uint64_t val;
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if (cat_cap_info.enabled) {
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for (i = 0U; i < platform_clos_num; i++) {
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switch (cat_cap_info.res_id) {
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case CAT_RESID_L2:
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msr_index = platform_l2_clos_array[i].msr_index;
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val = (uint64_t)platform_l2_clos_array[i].clos_mask;
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msr_write_pcpu(msr_index, val, pcpu_id);
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break;
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case CAT_RESID_L3:
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msr_index = platform_l3_clos_array[i].msr_index;
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val = (uint64_t)platform_l3_clos_array[i].clos_mask;
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msr_write_pcpu(msr_index, val, pcpu_id);
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break;
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default:
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pr_err("Invalid RDT resource configuration\n");
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}
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}
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/* set hypervisor CAT clos */
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msr_write_pcpu(MSR_IA32_PQR_ASSOC, clos2prq_msr(hv_clos), pcpu_id);
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}
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}
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uint64_t clos2prq_msr(uint16_t clos)
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{
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uint64_t prq_assoc;
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prq_assoc = msr_read(MSR_IA32_PQR_ASSOC);
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prq_assoc = (prq_assoc & 0xffffffffUL) | ((uint64_t)clos << 32U);
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return prq_assoc;
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}
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