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acrn-hypervisor/hypervisor/arch/x86
Vijay Dhanraj b8a021d658 HV: split L2 and L3 cache resource MSR
Upcoming intel platforms can support both L2 and L3
but our current code only supports either L2 or L3 CAT.
So split the MSRs so that we can support allocation
for both L2 and L3.

This patch does the following,
1. splits programming of L2 and L3 cache resource
based on the resource ID.
2. Replace generic platform_clos_array struct with resource
specific struct in all the existing board.c files.

Tracked-On: #3715
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-02-27 10:44:07 +08:00
..
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2020-02-25 09:08:14 +08:00
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