Shiqing Gao c0544c9d36 hv: treewide: fix 'Potential side effect problem in expression' ...

MISRA-C requirement:
The value of an expression shall be the same under any order of
evaluation.
The order in which side effects take place is unspecified and may lead
to unexpected results.

This patch add a temporary variable for temporary storage to avoid the
side effects of evaluation order.

Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>

2018-08-08 10:50:06 +08:00

..

console.c

hv:cleanup console/uart code

2018-08-02 11:25:40 +08:00

dump.c

vcpu: add get/set register APIs

2018-08-07 09:55:13 +08:00

logmsg.c

HV:fix rest integer violations

2018-08-02 09:51:58 +08:00

printf.c

hv: treewide: fix 'Potential side effect problem in expression'

2018-08-08 10:50:06 +08:00

sbuf.c

HV:fix rest integer violations

2018-08-02 09:51:58 +08:00

shell_internal.h

hv: treewide: fix 'Prototype and definition name mismatch'

2018-08-06 16:04:40 +08:00

shell.c

vcpu: add get/set register APIs

2018-08-07 09:55:13 +08:00

uart16550.c

hv:Rename port/mmio read and write APIs

2018-08-02 14:03:38 +08:00

uart16550.h

hv:cleanup console/uart code

2018-08-02 11:25:40 +08:00

vuart.c

hv:cleanup console/uart code

2018-08-02 11:25:40 +08:00