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There may be more than one PCI segment in target board, and DRHD info should be parsed correctly base on secondary PCI bus. currently board_parser.py tool did not handle such case. Add this patch for walking secondary PCI Bus. Tracked-On: #4143 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com>
14 KiB
14 KiB