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DCR is initialized to 0 which means divisor shift is 1. Currently, both are initialized to 0 which result in incorrect APIC timer counts if the vLAPIC's DCR is never programmed. This bug was exposed by OVMF because OVMF does not program DCR during LAPIC initialization. Tracked-On: #2543 Signed-off-by: Peter Fang <peter.fang@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>