Zide Chen ccfdf9cdd7 hv: nested: enable nested virtualization ... Allow guest set CR4_VMXE if CONFIG_NVMX_ENABLED is set: - move CR4_VMXE from CR4_EMULATED_RESERVE_BITS to CR4_TRAP_AND_EMULATE_BITS so that CR4_VMXE is removed from cr4_reserved_bits_mask. - force CR4_VMXE to be removed from cr4_rsv_bits_guest_value so that CR4_VMXE is able to be set. Expose VMX feature (CPUID01.01H:ECX[5]) to L1 guests whose GUEST_FLAG_NVMX_ENABLED is set. Assuming guest hypervisor (L1) is KVM, and KVM uses EPT for L2 guests. Constraints on ACRN VM. - LAPIC passthrough should be enabled. - use SCHED_NOOP scheduler. Tracked-On: #5923 Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com> Signed-off-by: Zide Chen <zide.chen@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>		2021-05-13 16:16:30 +08:00
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arch/x86/asm	hv: nested: enable nested virtualization	2021-05-13 16:16:30 +08:00
common	hv: hypercalls: refactor permission-checking and dispatching logic	2021-05-12 13:43:41 +08:00
debug	hv: mod: do not use explicit arch name when including headers	2021-05-08 11:15:46 +08:00
dm	hv: mod: do not use explicit arch name when including headers	2021-05-08 11:15:46 +08:00
hw	HV: deny HV owned PCI bar access from SOS	2021-02-03 14:01:23 +08:00
lib	hv: bugfix in min() and max() MACROs	2021-04-23 09:58:21 +08:00
public	config-tools: add NVMX_ENABLED feature and GUEST_FLAG_NVMX_ENABLED flag	2021-05-13 16:16:30 +08:00