Zide Chen ccfdf9cdd7 hv: nested: enable nested virtualization ... Allow guest set CR4_VMXE if CONFIG_NVMX_ENABLED is set: - move CR4_VMXE from CR4_EMULATED_RESERVE_BITS to CR4_TRAP_AND_EMULATE_BITS so that CR4_VMXE is removed from cr4_reserved_bits_mask. - force CR4_VMXE to be removed from cr4_rsv_bits_guest_value so that CR4_VMXE is able to be set. Expose VMX feature (CPUID01.01H:ECX[5]) to L1 guests whose GUEST_FLAG_NVMX_ENABLED is set. Assuming guest hypervisor (L1) is KVM, and KVM uses EPT for L2 guests. Constraints on ACRN VM. - LAPIC passthrough should be enabled. - use SCHED_NOOP scheduler. Tracked-On: #5923 Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com> Signed-off-by: Zide Chen <zide.chen@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>		2021-05-13 16:16:30 +08:00
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boot
guest	hv: nested: enable nested virtualization	2021-05-13 16:16:30 +08:00
lib
apicreg.h
board.h
cpu_caps.h
cpu.h
cpufeatures.h
cpuid.h
default_acpi_info.h
e820.h
gdt.h
host_pm.h
idt.h
init.h
io.h
ioapic.h
irq.h
lapic.h
mmu.h	hv: move invvpid and invept helper code from mmu.c to mmu.h	2021-05-13 16:16:30 +08:00
msr.h
notify.h
page.h
pci_dev.h
per_cpu.h
pgtable.h
platform_caps.h
rdt.h
rtcm.h
rtct.h
security.h
seed.h
sgx.h
timer.h
trampoline.h
vm_config.h
vmx.h
vtd.h
zeropage.h