mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-05-04 14:36:55 +00:00
bec21d147b
This adds few functions to access the daata structures defined inside ioapic.c. Removes the same data structures from ioapic.h Also this modifies some of the names of existing APIs to conform to the ioapic module name. Modified gsi_table identifier to gs_table_data, to avoid a MISRA C Violation. Tracked-On: #1842 Signed-off-by: Arindam Roy <arindam.roy@intel.com>
458 lines
10 KiB
C
458 lines
10 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <hypervisor.h>
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#include <ioapic.h>
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#define IOAPIC_MAX_PIN 240U
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#define IOAPIC_INVALID_PIN 0xffU
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/*
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* IOAPIC_MAX_LINES is architecturally defined.
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* The usable RTEs may be a subset of the total on a per IO APIC basis.
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*/
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#define IOAPIC_MAX_LINES 120U
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#define NR_MAX_GSI (NR_IOAPICS * IOAPIC_MAX_LINES)
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static struct gsi_table gsi_table_data[NR_MAX_GSI];
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static uint32_t ioapic_nr_gsi;
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static spinlock_t ioapic_lock;
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static union ioapic_rte saved_rte[NR_IOAPICS][IOAPIC_MAX_PIN];
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/*
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* the irq to ioapic pin mapping should extract from ACPI MADT table
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* hardcoded here
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*/
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static uint8_t legacy_irq_to_pin[NR_LEGACY_IRQ] = {
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2U, /* IRQ0*/
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1U, /* IRQ1*/
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0U, /* IRQ2 connected to Pin0 (ExtInt source of PIC) if existing */
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3U, /* IRQ3*/
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4U, /* IRQ4*/
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5U, /* IRQ5*/
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6U, /* IRQ6*/
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7U, /* IRQ7*/
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8U, /* IRQ8*/
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9U, /* IRQ9*/
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10U, /* IRQ10*/
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11U, /* IRQ11*/
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12U, /* IRQ12*/
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13U, /* IRQ13*/
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14U, /* IRQ14*/
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15U, /* IRQ15*/
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};
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static uint64_t legacy_irq_trigger_mode[NR_LEGACY_IRQ] = {
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IOAPIC_RTE_TRGREDG, /* IRQ0*/
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IOAPIC_RTE_TRGREDG, /* IRQ1*/
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IOAPIC_RTE_TRGREDG, /* IRQ2*/
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IOAPIC_RTE_TRGREDG, /* IRQ3*/
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IOAPIC_RTE_TRGREDG, /* IRQ4*/
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IOAPIC_RTE_TRGREDG, /* IRQ5*/
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IOAPIC_RTE_TRGREDG, /* IRQ6*/
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IOAPIC_RTE_TRGREDG, /* IRQ7*/
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IOAPIC_RTE_TRGREDG, /* IRQ8*/
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IOAPIC_RTE_TRGRLVL, /* IRQ9*/
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IOAPIC_RTE_TRGREDG, /* IRQ10*/
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IOAPIC_RTE_TRGREDG, /* IRQ11*/
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IOAPIC_RTE_TRGREDG, /* IRQ12*/
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IOAPIC_RTE_TRGREDG, /* IRQ13*/
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IOAPIC_RTE_TRGREDG, /* IRQ14*/
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IOAPIC_RTE_TRGREDG, /* IRQ15*/
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};
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const uint8_t pic_ioapic_pin_map[NR_LEGACY_PIN] = {
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2U, /* pin0*/
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1U, /* pin1*/
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0U, /* pin2*/
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3U, /* pin3*/
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4U, /* pin4*/
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5U, /* pin5*/
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6U, /* pin6*/
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7U, /* pin7*/
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8U, /* pin8*/
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9U, /* pin9*/
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10U, /* pin10*/
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11U, /* pin11*/
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12U, /* pin12*/
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13U, /* pin13*/
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14U, /* pin14*/
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15U, /* pin15*/
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};
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uint8_t get_pic_pin_from_ioapic_pin (uint8_t pin_index) {
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uint8_t pin_id = IOAPIC_INVALID_PIN;
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if (pin_index < NR_LEGACY_PIN) {
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pin_id = pic_ioapic_pin_map[pin_index];
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}
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return pin_id;
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}
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void *ioapic_get_gsi_irq_addr (uint32_t irq_num) {
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void *addr = NULL;
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if (irq_num < NR_MAX_GSI) {
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addr = gsi_table_data[irq_num].addr;
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}
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return addr;
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}
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uint32_t ioapic_get_nr_gsi (void) {
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return ioapic_nr_gsi;
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}
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static void *map_ioapic(uint64_t ioapic_paddr)
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{
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/* At some point we may need to translate this paddr to a vaddr.
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* 1:1 mapping for now.
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*/
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return hpa2hva(ioapic_paddr);
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}
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static inline uint32_t
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ioapic_read_reg32(void *ioapic_base, const uint32_t offset)
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{
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uint32_t v;
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uint64_t rflags;
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spinlock_irqsave_obtain(&ioapic_lock, &rflags);
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/* Write IOREGSEL */
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mmio_write32(offset, ioapic_base + IOAPIC_REGSEL);
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/* Read IOWIN */
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v = mmio_read32(ioapic_base + IOAPIC_WINDOW);
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spinlock_irqrestore_release(&ioapic_lock, rflags);
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return v;
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}
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static inline void
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ioapic_write_reg32(void *ioapic_base, const uint32_t offset, const uint32_t value)
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{
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uint64_t rflags;
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spinlock_irqsave_obtain(&ioapic_lock, &rflags);
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/* Write IOREGSEL */
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mmio_write32(offset, ioapic_base + IOAPIC_REGSEL);
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/* Write IOWIN */
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mmio_write32(value, ioapic_base + IOAPIC_WINDOW);
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spinlock_irqrestore_release(&ioapic_lock, rflags);
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}
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/**
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* @pre apic_id < 2
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*/
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static inline uint64_t
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get_ioapic_base(uint8_t apic_id)
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{
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const uint64_t addr[2] = {IOAPIC0_BASE, IOAPIC1_BASE};
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/* the ioapic base should be extracted from ACPI MADT table */
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return addr[apic_id];
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}
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void ioapic_get_rte_entry(void *ioapic_addr, uint8_t pin, union ioapic_rte *rte)
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{
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uint32_t rte_addr = ((uint32_t)pin * 2U) + 0x10U;
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rte->u.lo_32 = ioapic_read_reg32(ioapic_addr, rte_addr);
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rte->u.hi_32 = ioapic_read_reg32(ioapic_addr, rte_addr + 1U);
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}
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static inline void
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ioapic_set_rte_entry(void *ioapic_addr,
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uint8_t pin, union ioapic_rte rte)
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{
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uint32_t rte_addr = ((uint32_t)pin * 2U) + 0x10U;
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ioapic_write_reg32(ioapic_addr, rte_addr, rte.u.lo_32);
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ioapic_write_reg32(ioapic_addr, rte_addr + 1U, rte.u.hi_32);
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}
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static inline union ioapic_rte
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create_rte_for_legacy_irq(uint32_t irq, uint32_t vr)
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{
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union ioapic_rte rte;
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/* Legacy IRQ 0-15 setup, default masked
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* are actually defined in either MPTable or ACPI MADT table
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* before we have ACPI table parsing in HV we use common hardcode
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*/
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rte.full = IOAPIC_RTE_INTMSET;
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rte.full |= legacy_irq_trigger_mode[irq];
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rte.full |= DEFAULT_DEST_MODE;
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rte.full |= DEFAULT_DELIVERY_MODE;
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rte.full |= (IOAPIC_RTE_INTVEC & (uint64_t)vr);
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/* Fixed to active high */
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rte.full |= IOAPIC_RTE_INTAHI;
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/* Dest field: legacy irq fixed to CPU0 */
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rte.full |= (1UL << IOAPIC_RTE_DEST_SHIFT);
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return rte;
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}
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static inline union ioapic_rte
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create_rte_for_gsi_irq(uint32_t irq, uint32_t vr)
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{
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union ioapic_rte rte;
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if (irq < NR_LEGACY_IRQ) {
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rte = create_rte_for_legacy_irq(irq, vr);
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} else {
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/* irq default masked, level trig */
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rte.full = IOAPIC_RTE_INTMSET;
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rte.full |= IOAPIC_RTE_TRGRLVL;
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rte.full |= DEFAULT_DEST_MODE;
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rte.full |= DEFAULT_DELIVERY_MODE;
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rte.full |= (IOAPIC_RTE_INTVEC & (uint64_t)vr);
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/* Fixed to active high */
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rte.full |= IOAPIC_RTE_INTAHI;
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/* Dest field */
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rte.full |= (ALL_CPUS_MASK << IOAPIC_RTE_DEST_SHIFT);
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}
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return rte;
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}
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static void ioapic_set_routing(uint32_t gsi, uint32_t vr)
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{
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void *addr;
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union ioapic_rte rte;
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addr = gsi_table_data[gsi].addr;
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rte = create_rte_for_gsi_irq(gsi, vr);
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ioapic_set_rte_entry(addr, gsi_table_data[gsi].pin, rte);
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if ((rte.full & IOAPIC_RTE_TRGRMOD) != 0UL) {
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set_irq_trigger_mode(gsi, true);
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} else {
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set_irq_trigger_mode(gsi, false);
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}
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dev_dbg(ACRN_DBG_IRQ, "GSI: irq:%d pin:%hhu rte:%lx",
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gsi, gsi_table_data[gsi].pin,
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rte.full);
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}
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/**
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* @pre rte != NULL
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*/
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void ioapic_get_rte(uint32_t irq, union ioapic_rte *rte)
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{
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void *addr;
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if (ioapic_irq_is_gsi(irq)) {
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addr = gsi_table_data[irq].addr;
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ioapic_get_rte_entry(addr, gsi_table_data[irq].pin, rte);
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}
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}
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void ioapic_set_rte(uint32_t irq, union ioapic_rte rte)
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{
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void *addr;
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if (ioapic_irq_is_gsi(irq)) {
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addr = gsi_table_data[irq].addr;
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ioapic_set_rte_entry(addr, gsi_table_data[irq].pin, rte);
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dev_dbg(ACRN_DBG_IRQ, "GSI: irq:%d pin:%hhu rte:%lx",
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irq, gsi_table_data[irq].pin,
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rte.full);
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}
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}
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bool ioapic_irq_is_gsi(uint32_t irq)
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{
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return irq < ioapic_nr_gsi;
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}
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uint8_t ioapic_irq_to_pin(uint32_t irq)
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{
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uint8_t ret;
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if (ioapic_irq_is_gsi(irq)) {
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ret = gsi_table_data[irq].pin;
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} else {
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ret = IOAPIC_INVALID_PIN;
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}
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return ret;
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}
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bool ioapic_is_pin_valid (uint8_t pin) {
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return (pin != IOAPIC_INVALID_PIN);
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}
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uint32_t ioapic_pin_to_irq(uint8_t pin)
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{
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uint32_t i;
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uint32_t irq = IRQ_INVALID;
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for (i = 0U; i < ioapic_nr_gsi; i++) {
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if (gsi_table_data[i].pin == pin) {
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irq = i;
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break;
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}
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}
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return irq;
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}
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static void
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ioapic_irq_gsi_mask_unmask(uint32_t irq, bool mask)
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{
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void *addr = NULL;
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uint8_t pin;
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union ioapic_rte rte;
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if (ioapic_irq_is_gsi(irq)) {
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addr = gsi_table_data[irq].addr;
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pin = gsi_table_data[irq].pin;
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if (addr != NULL) {
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ioapic_get_rte_entry(addr, pin, &rte);
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if (mask) {
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rte.full |= IOAPIC_RTE_INTMSET;
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} else {
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rte.full &= ~IOAPIC_RTE_INTMASK;
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}
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ioapic_set_rte_entry(addr, pin, rte);
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dev_dbg(ACRN_DBG_PTIRQ, "update: irq:%d pin:%hhu rte:%lx",
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irq, pin, rte.full);
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} else {
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dev_dbg(ACRN_DBG_PTIRQ, "NULL Address returned from gsi_table_data");
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}
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}
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}
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void ioapic_gsi_mask_irq(uint32_t irq)
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{
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ioapic_irq_gsi_mask_unmask(irq, true);
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}
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void ioapic_gsi_unmask_irq(uint32_t irq)
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{
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ioapic_irq_gsi_mask_unmask(irq, false);
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}
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static uint8_t
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ioapic_nr_pins(void *ioapic_base)
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{
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uint32_t version;
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uint8_t nr_pins;
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version = ioapic_read_reg32(ioapic_base, IOAPIC_VER);
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dev_dbg(ACRN_DBG_IRQ, "IOAPIC version: %x", version);
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/* The 23:16 bits in the version register is the highest entry in the
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* I/O redirection table, which is 1 smaller than the number of
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* interrupt input pins. */
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nr_pins = (uint8_t)
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(((version & IOAPIC_MAX_RTE_MASK) >> MAX_RTE_SHIFT) + 1U);
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ASSERT(nr_pins > NR_LEGACY_IRQ, "Legacy IRQ num > total GSI");
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ASSERT(nr_pins <= IOAPIC_MAX_PIN, "IOAPIC pins exceeding 240");
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return nr_pins;
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}
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void ioapic_setup_irqs(void)
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{
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uint8_t ioapic_id;
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uint32_t gsi = 0U;
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uint32_t vr;
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spinlock_init(&ioapic_lock);
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for (ioapic_id = 0U;
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ioapic_id < NR_IOAPICS; ioapic_id++) {
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void *addr;
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uint8_t pin, nr_pins;
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addr = map_ioapic(get_ioapic_base(ioapic_id));
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hv_access_memory_region_update((uint64_t)addr, PAGE_SIZE);
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nr_pins = ioapic_nr_pins(addr);
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for (pin = 0U; pin < nr_pins; pin++) {
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gsi_table_data[gsi].ioapic_id = ioapic_id;
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gsi_table_data[gsi].addr = addr;
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if (gsi < NR_LEGACY_IRQ) {
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gsi_table_data[gsi].pin =
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legacy_irq_to_pin[gsi] & 0xffU;
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} else {
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gsi_table_data[gsi].pin = pin;
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}
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/* pinned irq before use it */
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if (alloc_irq_num(gsi) == IRQ_INVALID) {
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pr_err("failed to alloc IRQ[%d]", gsi);
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gsi++;
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continue;
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}
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/* assign vector for this GSI
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* for legacy irq, reserved vector and never free
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*/
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if (gsi < NR_LEGACY_IRQ) {
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vr = alloc_irq_vector(gsi);
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if (vr == VECTOR_INVALID) {
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pr_err("failed to alloc VR");
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gsi++;
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continue;
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}
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} else {
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vr = 0U; /* not to allocate VR right now */
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}
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ioapic_set_routing(gsi, vr);
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gsi++;
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}
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}
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/* system max gsi numbers */
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ioapic_nr_gsi = gsi;
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ASSERT(ioapic_nr_gsi <= NR_MAX_GSI, "GSI table overflow");
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}
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void suspend_ioapic(void)
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{
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uint8_t ioapic_id, ioapic_pin;
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for (ioapic_id = 0U; ioapic_id < NR_IOAPICS; ioapic_id++) {
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void *addr;
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uint8_t nr_pins;
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addr = map_ioapic(get_ioapic_base(ioapic_id));
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nr_pins = ioapic_nr_pins(addr);
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for (ioapic_pin = 0U; ioapic_pin < nr_pins; ioapic_pin++) {
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ioapic_get_rte_entry(addr, ioapic_pin,
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&saved_rte[ioapic_id][ioapic_pin]);
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}
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}
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}
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void resume_ioapic(void)
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{
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uint8_t ioapic_id, ioapic_pin;
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for (ioapic_id = 0U; ioapic_id < NR_IOAPICS; ioapic_id++) {
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void *addr;
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uint8_t nr_pins;
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addr = map_ioapic(get_ioapic_base(ioapic_id));
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nr_pins = ioapic_nr_pins(addr);
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for (ioapic_pin = 0U; ioapic_pin < nr_pins; ioapic_pin++) {
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ioapic_set_rte_entry(addr, ioapic_pin,
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saved_rte[ioapic_id][ioapic_pin]);
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}
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}
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}
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