github/acrn-hypervisor
1
0
Fork 0
mirror of https://github.com/projectacrn/acrn-hypervisor.git synced 2025-06-03 20:59:53 +00:00
Code Issues Projects Releases Wiki Activity
d43d2c9295
acrn-hypervisor/hypervisor/include/arch
History
Yonghua Huang d43d2c9295 HV: add CPU capabilities detection for L1TF mitigation 
- detect if current processor is affected by L1TF
  - detect the presence of of "IA32_FLUSH_CMD(MSR 0x10B)
    if processor is affected by L1TF.

Tracked-On: #1672
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
2018-11-01 11:21:15 +08:00
..
x86 HV: add CPU capabilities detection for L1TF mitigation 2018-11-01 11:21:15 +08:00