mirror of
https://github.com/projectacrn/acrn-hypervisor.git
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d0e06c4f80
New board, EHL CRB, does not have legacy port IO UART. Even the PCI UART are not work due to BIOS's bug workaround(the BARs on LPSS PCI are reset after BIOS hand over control to OS). For ACRN console usage, expose the debug UART via ACPI PnP device (access by MMIO) and add support in hypervisor debug code. Another special thing is that register width of UART of EHL CRB is 1byte. Introduce reg_width for each struct console_uart. Tracked-On: #4937 Signed-off-by: Yin Fengwei <fengwei.yin@intel.com> Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
64 lines
1.4 KiB
C
64 lines
1.4 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <types.h>
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#include <rtl.h>
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#include <pci.h>
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#include <uart16550.h>
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#include <dbg_cmd.h>
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#define MAX_PORT 0x10000 /* port 0 - 64K */
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#define DEFAULT_UART_PORT 0x3F8
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#define MAX_CMD_LEN 64
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static struct uart_cmd {
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const char *const str;
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int type;
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} cmd_list[] = {
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{ "uart=port@", PIO }, /* uart=port@0x3F8 */
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{ "uart=bdf@", PCI }, /* uart=bdf@0:18.2 */
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{ "uart=mmio@", MMIO }, /* uart=mmio@0xfe040000 */
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{ "uart=disabled", INVALID }
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};
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bool handle_dbg_cmd(const char *cmd, int32_t len)
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{
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uint32_t i;
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for (i = 0; i < ARRAY_SIZE(cmd_list); i++) {
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int32_t tmp = strnlen_s(cmd_list[i].str, MAX_CMD_LEN);
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int type = cmd_list[i].type;
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/* cmd prefix should be same with one in cmd_list */
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if (len < tmp)
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continue;
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if (strncmp(cmd_list[i].str, cmd, tmp) != 0)
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continue;
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if (type == INVALID) {
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/* set uart disabled*/
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uart16550_set_property(false, type, 0UL);
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} else if (type == PIO) {
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uint64_t addr = strtoul_hex(cmd + tmp);
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if (addr > MAX_PORT) {
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addr = DEFAULT_UART_PORT;
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}
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uart16550_set_property(true, type, addr);
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} else if (type == PCI) {
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uart16550_set_property(true, type, (uint64_t)(cmd+tmp));
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} else {
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uint64_t addr = strtoul_hex(cmd + tmp);
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uart16550_set_property(true, type, addr);
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}
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}
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return i < ARRAY_SIZE(cmd_list)? true : false;
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}
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