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ab4e19d0be
The current code would write 'BAR address & size_maks' into PCIe virtual BAR before updating the virtual BAR's base address when guest writing a PCIe device's BAR. If the size of a PCIe device's BAR is larger than 4G, the low 32 bits size_mask for this 64 bits BAR is zero. When ACRN updating the virtual BAR's base address, the low 32 bits sizing information would be lost. This patch saves whether a BAR writing is sizing or not before updating the virtual BAR's base address. Tracked-On: #8267 Signed-off-by: Fei Li <fei1.li@intel.com>