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4c0965d89e
Currently ept_pages_info[] is initialized with first element only that force VM of id 0 using SOS EPT pages. This is incorrect for logical partition and hybrid scenario. Considering SOS_RAM_SIZE and UOS_RAM_SIZE are configured separately, we should use different ept pages accordingly. So, the PRE_VM_NUM/SOS_VM_NUM and MAX_POST_VM_NUM macros are introduced to resolve this issue. The macros would be generated by acrn-config tool when user configure ACRN for their specific scenario. One more thing, that when UOS_RAM_SIZE is less then 2GB, the EPT address range should be (4G + PLATFORM_HI_MMIO_SIZE). Tracked-On: #4458 Signed-off-by: Victor Sun <victor.sun@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
42 lines
1.2 KiB
C
42 lines
1.2 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef VM_CONFIGURATIONS_H
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#define VM_CONFIGURATIONS_H
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#include <misc_cfg.h>
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/* SOS_VM_NUM can only be 0U or 1U;
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* When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too;
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* MAX_POST_VM_NUM must be bigger than CONFIG_MAX_KATA_VM_NUM;
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*/
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#define PRE_VM_NUM 0U
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#define SOS_VM_NUM 1U
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#define MAX_POST_VM_NUM 3U
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/* Bits mask of guest flags that can be programmed by device model. Other bits are set by hypervisor only */
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#define DM_OWNED_GUEST_FLAG_MASK (GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | \
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GUEST_FLAG_RT | GUEST_FLAG_IO_COMPLETION_POLLING)
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#define SOS_VM_BOOTARGS SOS_ROOTFS \
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"rw rootwait " \
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"console=tty0 " \
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SOS_CONSOLE \
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"consoleblank=0 " \
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"no_timer_check " \
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"quiet loglevel=3 " \
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"i915.nuclear_pageflip=1 " \
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"i915.avail_planes_per_pipe=0x01010F " \
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"i915.domain_plane_owners=0x011111110000 " \
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"i915.enable_gvt=1 idle=halt " \
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SOS_BOOTARGS_DIFF
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#define VM1_CONFIG_VCPU_AFFINITY {AFFINITY_CPU(1U)}
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#define VM2_CONFIG_VCPU_AFFINITY {AFFINITY_CPU(2U)}
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#define VM3_CONFIG_VCPU_AFFINITY {AFFINITY_CPU(3U)}
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#endif /* VM_CONFIGURATIONS_H */
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