Arindam Roy dbfd0e5b67 HV: Fix missing brackets for MISRA C Violations ...

Patch 2 of 7.
Added changes to make sure Misra C violations are fixed
for rules 11S and 12S.

Signed-off-by: Arindam Roy <arindam.roy@intel.com>

2018-07-13 09:09:12 +08:00

..

guest.c

HV: Fix missing brackets for MISRA C Violations

2018-07-13 09:09:12 +08:00

instr_emul_wrapper.c

HV: instr_emul: Rename emul_cnx to emul_ctxt

2018-07-09 09:27:42 +08:00

instr_emul_wrapper.h

HV: instr_emul: Rename emul_cnx to emul_ctxt

2018-07-09 09:27:42 +08:00

instr_emul.c

HV: Fix missing brackets for MISRA C Violations

2018-07-13 09:09:12 +08:00

instr_emul.h

HV: instr_emul: enforce unsignedness when possible

2018-07-05 13:14:07 +08:00

pm.c

HV: pm: cleanup for misra integral type violations

2018-07-12 17:31:11 +08:00

ucode.c

HV: Avoiding the chained assignment

2018-07-10 11:49:50 +08:00

vcpu.c

HV:treewide:Add 16-bit atomic operations and update vpid type

2018-07-11 21:27:08 +08:00

vioapic.c

HV: add the missing brackets to loop body

2018-07-12 17:27:29 +08:00

vlapic_priv.h

hv:merge struct lapic and lapic_regs to lapic_regs

2018-07-02 10:49:14 +08:00

vlapic.c

HV: add the missing brackets to loop body

2018-07-12 17:27:29 +08:00

vm.c

HV: add the missing brackets to loop body

2018-07-12 17:27:29 +08:00

vmcall.c

HV: Make all trace event prefix consist with TRACE

2018-07-02 10:46:41 +08:00

vmsr.c

HV: code cleanup as MISRA-C report for guest/vmsr

2018-07-12 17:27:53 +08:00

vpic.c

HV:treewide:Update return type of function ffs64 and ffz64

2018-07-02 15:11:22 +08:00