Li Fei1 e99ddf28c3 hv: vpci: handle the quirk part for pass through pci device cfg access in dm ... There're some PCI devices need special handler for vendor-specical feature or capability CFG access. The Intel GPU is one of them. In order to keep the ACRN-HV clean, we want to throw the qurik part of PCI CFG asccess to DM to handle. To achieve this, we implement per-device policy base on whether it needs quirk handler for a VM: each device could configure as "quirk pass through device" or not. For a "quirk pass through device", we will handle the general part in HV and the quirk part in DM. For a non "quirk pass through device", we will handle all the part in HV. Tracked-On: #4371 Signed-off-by: Li Fei1 <fei1.li@intel.com>		2020-03-20 10:08:43 +08:00
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arch/x86	hv: vpci: sos could access low severity guest pci cfg space	2020-03-20 10:08:43 +08:00
common	hv: Variable/macro renaming for intr handling of PT devices using IO-APIC/PIC	2020-03-06 11:29:02 +08:00
debug	HV: correct ept page array usage	2020-03-12 14:56:34 +08:00
dm	hv: vpci: handle the quirk part for pass through pci device cfg access in dm	2020-03-20 10:08:43 +08:00
hw	hv: vpci: handle the quirk part for pass through pci device cfg access in dm	2020-03-20 10:08:43 +08:00
lib	hv: support xsave in context switch	2019-12-02 09:31:12 +08:00
public	hv: vpci: handle the quirk part for pass through pci device cfg access in dm	2020-03-20 10:08:43 +08:00