Sainath Grandhi ef03385f42 hv: Write Buffer Flush - VT-d ... This patch does the following changes According to VT-d spec Section 6.8 "Write Buffer Flushing" DRAM write buffers are flushed implicitly upon Remapping Hardware Caches Invalidation even on platforms that set RWBF to 1 in capability register. So removed write buffer flushing as current ACRN issues cache invalidation commands in all cases. Tracked-On: #1855 Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>		2018-12-24 22:18:30 +08:00
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x86	hv: Write Buffer Flush - VT-d	2018-12-24 22:18:30 +08:00