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3547c9cd23
x86/timer.[ch] was moved to the common directory largely unchanged. x86 specific code now resides in x86/tsc_deadline_timer.c and its interface was defined in hw/hw_timer.h. The interface defines two functions: init_hw_timer() and set_hw_timeout() that provides HW specific initialization and timer interrupt source. Other than these two functions, the timer module is largely arch agnostic. Tracked-On: #5920 Signed-off-by: Rong Liu <rong2.liu@intel.com> Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
51 lines
1.1 KiB
C
51 lines
1.1 KiB
C
/*
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* Copyright (C) 2021 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <types.h>
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#include <softirq.h>
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#include <irq.h>
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#include <logmsg.h>
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#include <asm/cpu.h>
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#include <asm/msr.h>
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#include <asm/irq.h>
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#include <asm/apicreg.h>
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#include <hw/hw_timer.h>
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/* run in interrupt context */
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static void timer_expired_handler(__unused uint32_t irq, __unused void *data)
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{
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fire_softirq(SOFTIRQ_TIMER);
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}
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void set_hw_timeout(uint64_t timeout)
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{
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msr_write(MSR_IA32_TSC_DEADLINE, timeout);
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}
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void init_hw_timer(void)
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{
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int32_t retval = 0;
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if (get_pcpu_id() == BSP_CPU_ID) {
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retval = request_irq(TIMER_IRQ, (irq_action_t)timer_expired_handler, NULL, IRQF_NONE);
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if (retval < 0) {
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pr_err("Timer setup failed");
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}
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}
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if (retval >= 0) {
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uint32_t val = TIMER_VECTOR;
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val |= APIC_LVTT_TM_TSCDLT; /* TSC deadline and unmask */
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msr_write(MSR_IA32_EXT_APIC_LVT_TIMER, val);
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/* SDM 10.5.4.1: In x2APIC mode, the processor ensures the
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ordering of this write and any subsequent WRMSR to the
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deadline; no fencing is required. */
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/* disarm timer */
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msr_write(MSR_IA32_TSC_DEADLINE, 0UL);
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}
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}
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