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https://github.com/projectacrn/acrn-hypervisor.git
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f5744174b5
This patch emulates the VMPTRLD instruction. L0 hypervisor (ACRN) caches the VMCS12 that is passed down from the VMPTRLD instruction, and merges it with VMCS01 to create VMCS02 to run the nested VM. - Currently ACRN can't cache multiple VMCS12 on one vCPU, so it needs to flushes active but not current VMCS12s to L1 guest. - ACRN creates VMCS02 to run nested VM based on VMCS12: 1) copy VMCS12 from guest memory to the per vCPU cache VMCS12 2) initialize VMCS02 revision ID and host-state area 3) load shadow fields from cache VMCS12 to VMCS02 4) enable VMCS shadowing before L1 Vm entry Tracked-On: #5923 Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com> Signed-off-by: Zide Chen <zide.chen@intel.com>
131 lines
3.9 KiB
C
131 lines
3.9 KiB
C
/*
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* Copyright (C) 2021 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef NESTED_H
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#define NESTED_H
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#include <lib/errno.h>
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/* helper data structure to make VMX capability MSR manipulation easier */
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union value_64 {
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uint64_t full;
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struct {
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uint32_t lo_32;
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uint32_t hi_32;
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} u;
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};
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/*
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* Following MSRs are supported if nested virtualization is enabled
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* - If CONFIG_NVMX_ENABLED is set, these MSRs are included in emulated_guest_msrs[]
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* - otherwise, they are included in unsupported_msrs[]
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*/
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#define NUM_VMX_MSRS 20U
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#define LIST_OF_VMX_MSRS \
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MSR_IA32_SMBASE, \
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MSR_IA32_VMX_BASIC, \
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MSR_IA32_VMX_PINBASED_CTLS, \
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MSR_IA32_VMX_PROCBASED_CTLS, \
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MSR_IA32_VMX_EXIT_CTLS, \
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MSR_IA32_VMX_ENTRY_CTLS, \
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MSR_IA32_VMX_MISC, \
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MSR_IA32_VMX_CR0_FIXED0, \
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MSR_IA32_VMX_CR0_FIXED1, \
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MSR_IA32_VMX_CR4_FIXED0, \
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MSR_IA32_VMX_CR4_FIXED1, \
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MSR_IA32_VMX_VMCS_ENUM, \
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MSR_IA32_VMX_PROCBASED_CTLS2, \
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MSR_IA32_VMX_EPT_VPID_CAP, \
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MSR_IA32_VMX_TRUE_PINBASED_CTLS, \
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MSR_IA32_VMX_TRUE_PROCBASED_CTLS, \
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MSR_IA32_VMX_TRUE_EXIT_CTLS, \
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MSR_IA32_VMX_TRUE_ENTRY_CTLS, \
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MSR_IA32_VMX_VMFUNC, \
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MSR_IA32_VMX_PROCBASED_CTLS3
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/*
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* VM-Exit Instruction-Information Field
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*
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* ISDM Vol 3C Table 27-9: INVEPT, INVPCID, INVVPID
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* ISDM Vol 3C Table 27-13: VMCLEAR, VMPTRLD, VMPTRST, VMXON, XRSTORS, and XSAVES.
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* ISDM Vol 3C Table 27-14: VMREAD and VMWRITE
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*
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* Either Table 27-9 or Table 27-13 is a subset of Table 27-14, so we are able to
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* define the following macros to be used for the above mentioned instructions.
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*/
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#define VMX_II_SCALING(v) (((v) >> 0U) & 0x3U)
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#define VMX_II_REG1(v) (((v) >> 3U) & 0xfU)
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#define VMX_II_ADDR_SIZE(v) (((v) >> 7U) & 0x7U)
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#define VMX_II_IS_REG(v) (((v) >> 10U) & 0x1U)
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#define VMX_II_SEG_REG(v) (((v) >> 15U) & 0x7U)
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#define VMX_II_IDX_REG(v) (((v) >> 18U) & 0xfU)
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#define VMX_II_IDX_REG_VALID(v) ((((v) >> 22U) & 0x1U) == 0U)
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#define VMX_II_BASE_REG(v) (((v) >> 23U) & 0xfU)
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#define VMX_II_BASE_REG_VALID(v) ((((v) >> 27U) & 0x1U) == 0U)
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#define VMX_II_REG2(v) (((v) >> 28U) & 0xfU)
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#define VMCS_SHADOW_BIT_INDICATOR (1U << 31U)
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/* refer to ISDM: Table 30-1. VM-Instruction Error Numbers */
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#define VMXERR_VMPTRLD_INVALID_ADDRESS (9)
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#define VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID (10)
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#define VMXERR_VMPTRLD_VMXON_POINTER (11)
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#define VMXERR_VMXON_IN_VMX_ROOT_OPERATION (15)
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/*
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* This VMCS12 revision id is chosen arbitrarily.
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* The emulated MSR_IA32_VMX_BASIC returns this ID in bits 30:0.
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*/
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#define VMCS12_REVISION_ID 0x15407E12U
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/* Implemented in next patch */
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struct acrn_vmcs12 {};
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enum VMXResult {
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VMsucceed,
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VMfailValid,
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VMfailInvalid,
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};
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void nested_vmx_result(enum VMXResult, int error_number);
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int32_t vmxon_vmexit_handler(struct acrn_vcpu *vcpu);
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int32_t vmxoff_vmexit_handler(struct acrn_vcpu *vcpu);
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int32_t vmptrld_vmexit_handler(struct acrn_vcpu *vcpu);
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#ifdef CONFIG_NVMX_ENABLED
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struct acrn_nested {
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uint8_t vmcs02[PAGE_SIZE]; /* VMCS to run L2 and as Link Pointer in VMCS01 */
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struct acrn_vmcs12 vmcs12; /* To cache L1's VMCS12*/
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uint64_t current_vmcs12_ptr; /* GPA */
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uint64_t vmxon_ptr; /* GPA */
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bool vmxon; /* To indicate if vCPU entered VMX operation */
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} __aligned(PAGE_SIZE);
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void init_nested_vmx(__unused struct acrn_vm *vm);
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bool is_vmx_msr(uint32_t msr);
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void init_vmx_msrs(struct acrn_vcpu *vcpu);
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int32_t read_vmx_msr(__unused struct acrn_vcpu *vcpu, uint32_t msr, uint64_t *val);
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#else
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struct acrn_nested {};
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static inline void init_nested_vmx(__unused struct acrn_vm *vm) {}
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static inline bool is_vmx_msr(__unused uint32_t msr)
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{
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/*
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* if nested virtualization is disabled, return false so that
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* it can be treated as unsupported MSR.
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*/
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return false;
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}
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static inline void init_vmx_msrs(__unused struct acrn_vcpu *vcpu) {}
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static inline int32_t read_vmx_msr(__unused struct acrn_vcpu *vcpu,
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__unused uint32_t msr, __unused uint64_t *val)
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{
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return -EACCES;
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}
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#endif /* CONFIG_NVMX_ENABLED */
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#endif /* NESTED_H */
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