mirror of
https://github.com/projectacrn/acrn-hypervisor.git
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99f15a27c2
This patch adds support to parse RTCT v2 using the refined board XML schema. The major changes include: - Add the RTCT v2 parser in the acpiparser module. The version of an RTCT is detected automatically to choose the right parser. - Extract software SRAM capabilities of caches into the board XML. - Move the logic that determines the software SRAM base address for the pre-launched VM to the static allocator of GPAs. - Generate software SRAM related macros into misc_cfg.h when necessary. Tracked-On: #6020 Signed-off-by: Junjie Mao <junjie.mao@intel.com>
293 lines
9.9 KiB
Python
293 lines
9.9 KiB
Python
# Copyright (C) 2021 Intel Corporation. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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import ctypes
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import copy
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import lib.cdata as cdata
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from acpiparser._utils import TableHeader
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# Common structures
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class RTCTSubtable(cdata.Struct):
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_pack_ = 1
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_fields_ = [
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('subtable_size', ctypes.c_uint16),
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('format', ctypes.c_uint16),
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('type', ctypes.c_uint32),
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]
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ACPI_RTCT_TYPE_COMPATIBILITY = 0
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class RTCTSubtableCompatibility(cdata.Struct):
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_pack_ = 1
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_fields_ = copy.copy(RTCTSubtable._fields_) + [
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('rtct_version_major', ctypes.c_uint32),
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('rtct_version_minor', ctypes.c_uint32),
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('rtcd_version_major', ctypes.c_uint32),
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('rtcd_version_minor', ctypes.c_uint32),
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]
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def RTCTSubtableUnknown_factory(data_len):
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class RTCTSubtableUnknown(cdata.Struct):
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_pack_ = 1
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_fields_ = copy.copy(RTCTSubtable._fields_) + [
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('data', ctypes.c_uint8 * data_len),
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]
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return RTCTSubtableUnknown
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# RTCT v1
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ACPI_RTCT_V1_TYPE_RTCM_BINARY = 2
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ACPI_RTCT_V1_TYPE_WRC_L3Waymasks = 3
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ACPI_RTCT_V1_TYPE_GT_L3Waymasks = 4
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ACPI_RTCT_V1_TYPE_SoftwareSRAM = 5
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ACPI_RTCT_V1_TYPE_Memory_Hierarchy_Latency = 9
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class RTCTSubtableRTCMBinary(cdata.Struct):
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_pack_ = 1
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_fields_ = copy.copy(RTCTSubtable._fields_) + [
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('address', ctypes.c_uint64),
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('size', ctypes.c_uint32),
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]
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def RTCTSubtableWRCL3Waymasks_factory(data_len):
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class RTCTSubtableWRCL3Waymasks(cdata.Struct):
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_pack_ = 1
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_fields_ = copy.copy(RTCTSubtable._fields_) + [
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('waymask', ctypes.c_uint32 * (data_len // 4)),
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]
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return RTCTSubtableWRCL3Waymasks
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def RTCTSubtableGTL3Waymasks_factory(data_len):
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class RTCTSubtableGTL3Waymasks(cdata.Struct):
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_pack_ = 1
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_fields_ = copy.copy(RTCTSubtable._fields_) + [
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('waymask', ctypes.c_uint32 * (data_len // 4)),
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]
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return RTCTSubtableGTL3Waymasks
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def RTCTSubtableSoftwareSRAM_v1_factory(data_len):
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class RTCTSubtableSoftwareSRAM_v1(cdata.Struct):
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_pack_ = 1
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_fields_ = copy.copy(RTCTSubtable._fields_) + [
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('cache_level', ctypes.c_uint32),
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('base', ctypes.c_uint64),
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('ways', ctypes.c_uint32),
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('size', ctypes.c_uint32),
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('apic_id_tbl', ctypes.c_uint32 * ((data_len - 20) // 4)),
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]
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return RTCTSubtableSoftwareSRAM_v1
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def RTCTSubtableMemoryHierarchyLatency_v1_factory(data_len):
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class RTCTSubtableMemoryHierarchyLatency_v1(cdata.Struct):
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_pack_ = 1
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_fields_ = copy.copy(RTCTSubtable._fields_) + [
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('hierarchy', ctypes.c_uint32),
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('clock_cycles', ctypes.c_uint32),
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('apic_id_tbl', ctypes.c_uint32 * ((data_len - 8) // 4)),
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]
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return RTCTSubtableMemoryHierarchyLatency_v1
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# RTCT v2
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ACPI_RTCT_V2_TYPE_RTCD_Limits = 1
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ACPI_RTCT_V2_TYPE_CRL_Binary = 2
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ACPI_RTCT_V2_TYPE_IA_WayMasks = 3
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ACPI_RTCT_V2_TYPE_WRC_WayMasks = 4
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ACPI_RTCT_V2_TYPE_GT_WayMasks = 5
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ACPI_RTCT_V2_TYPE_SSRAM_WayMask = 6
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ACPI_RTCT_V2_TYPE_SoftwareSRAM = 7
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ACPI_RTCT_V2_TYPE_MemoryHierarchyLatency = 8
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ACPI_RTCT_V2_TYPE_ErrorLogAddress = 9
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class RTCTSubtableRTCDLimits(cdata.Struct):
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_pack_ = 1
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_fields_ = copy.copy(RTCTSubtable._fields_) + [
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('total_ia_l2_clos', ctypes.c_uint32),
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('total_ia_l3_clos', ctypes.c_uint32),
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('total_l2_instances', ctypes.c_uint32),
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('total_l3_instances', ctypes.c_uint32),
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('total_gt_clos', ctypes.c_uint32),
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('total_wrc_clos', ctypes.c_uint32),
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('max_tcc_streams', ctypes.c_uint32),
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('max_tcc_registers', ctypes.c_uint32),
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]
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def RTCTSubtableIAWayMasks_factory(data_len):
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class RTCTSubtableIAWayMasks(cdata.Struct):
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_pack_ = 1
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_fields_ = copy.copy(RTCTSubtable._fields_) + [
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('level', ctypes.c_uint32),
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('cache_id', ctypes.c_uint32),
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('waymask', ctypes.c_uint32 * ((data_len - 8) // 4)),
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]
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return RTCTSubtableIAWayMasks
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class RTCTSubtableWRCWayMasks(cdata.Struct):
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_pack_ = 1
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_fields_ = copy.copy(RTCTSubtable._fields_) + [
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('level', ctypes.c_uint32),
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('cache_id', ctypes.c_uint32),
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('waymask', ctypes.c_uint32),
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]
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def RTCTSubtableGTWayMasks_factory(data_len):
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class RTCTSubtableGTWayMasks(cdata.Struct):
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_pack_ = 1
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_fields_ = copy.copy(RTCTSubtable._fields_) + [
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('level', ctypes.c_uint32),
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('cache_id', ctypes.c_uint32),
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('waymask', ctypes.c_uint32 * ((data_len - 8) // 4)),
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]
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return RTCTSubtableGTWayMasks
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class RTCTSubtableSSRAMWayMask(cdata.Struct):
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_pack_ = 1
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_fields_ = copy.copy(RTCTSubtable._fields_) + [
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('level', ctypes.c_uint32),
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('cache_id', ctypes.c_uint32),
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('waymask', ctypes.c_uint32),
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]
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def RTCTSubtableSoftwareSRAM_v2_factory(data_len):
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class RTCTSubtableSoftwareSRAM_v2(cdata.Struct):
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_pack_ = 1
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_fields_ = copy.copy(RTCTSubtable._fields_) + [
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('level', ctypes.c_uint32),
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('cache_id', ctypes.c_uint32),
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('base', ctypes.c_uint64),
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('size', ctypes.c_uint32),
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('shared', ctypes.c_uint32),
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]
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return RTCTSubtableSoftwareSRAM_v2
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def RTCTSubtableMemoryHierarchyLatency_v2_factory(data_len):
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class RTCTSubtableMemoryHierarchyLatency_v2(cdata.Struct):
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_pack_ = 1
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_fields_ = copy.copy(RTCTSubtable._fields_) + [
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('hierarchy', ctypes.c_uint32),
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('clock_cycles', ctypes.c_uint32),
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('cache_id', ctypes.c_uint32 * ((data_len - 8) // 4)),
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]
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return RTCTSubtableMemoryHierarchyLatency_v2
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class RTCTSubtableErrorLogAddress(cdata.Struct):
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_pack_ = 1
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_fields_ = copy.copy(RTCTSubtable._fields_) + [
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('address', ctypes.c_uint64),
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('size', ctypes.c_uint32),
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]
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# Parsers
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def rtct_version(addr, length):
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end = addr + length
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while addr < end:
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subtable = RTCTSubtable.from_address(addr)
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if subtable.type == ACPI_RTCT_TYPE_COMPATIBILITY:
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subtable = RTCTSubtableCompatibility.from_address(addr)
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return subtable.rtct_version_major
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addr += subtable.subtable_size
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# RTCT v1 does not have a compatibility entry
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return 1
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def rtct_v1_subtable_list(addr, length):
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end = addr + length
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field_list = list()
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subtable_num = 0
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while addr < end:
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subtable_num += 1
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subtable = RTCTSubtable.from_address(addr)
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data_len = subtable.subtable_size - ctypes.sizeof(RTCTSubtable)
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if subtable.type == ACPI_RTCT_V1_TYPE_RTCM_BINARY:
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cls = RTCTSubtableRTCMBinary
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elif subtable.type == ACPI_RTCT_V1_TYPE_WRC_L3Waymasks:
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cls = RTCTSubtableWRCL3Waymasks_factory(data_len)
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elif subtable.type == ACPI_RTCT_V1_TYPE_GT_L3Waymasks:
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cls = RTCTSubtableGTL3Waymasks_factory(data_len)
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elif subtable.type == ACPI_RTCT_V1_TYPE_SoftwareSRAM:
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cls = RTCTSubtableSoftwareSRAM_v1_factory(data_len)
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elif subtable.type == ACPI_RTCT_V1_TYPE_Memory_Hierarchy_Latency:
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cls = RTCTSubtableMemoryHierarchyLatency_v1_factory(data_len)
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else:
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cls = RTCTSubtableUnknown_factory(data_len)
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addr += subtable.subtable_size
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field_list.append( ('subtable{}'.format(subtable_num), cls) )
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return field_list
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def rtct_v2_subtable_list(addr, length):
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end = addr + length
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field_list = list()
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subtable_num = 0
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while addr < end:
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subtable_num += 1
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subtable = RTCTSubtable.from_address(addr)
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data_len = subtable.subtable_size - ctypes.sizeof(RTCTSubtable)
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if subtable.type == ACPI_RTCT_V2_TYPE_RTCD_Limits:
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cls = RTCTSubtableRTCDLimits
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elif subtable.type == ACPI_RTCT_V2_TYPE_CRL_Binary:
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cls = RTCTSubtableRTCMBinary
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elif subtable.type == ACPI_RTCT_V2_TYPE_IA_WayMasks:
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cls = RTCTSubtableIAWayMasks_factory(data_len)
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elif subtable.type == ACPI_RTCT_V2_TYPE_WRC_WayMasks:
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cls = RTCTSubtableWRCWayMasks
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elif subtable.type == ACPI_RTCT_V2_TYPE_GT_WayMasks:
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cls = RTCTSubtableGTWayMasks_factory(data_len)
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elif subtable.type == ACPI_RTCT_V2_TYPE_SSRAM_WayMask:
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cls = RTCTSubtableSSRAMWayMask
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elif subtable.type == ACPI_RTCT_V2_TYPE_SoftwareSRAM:
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cls = RTCTSubtableSoftwareSRAM_v2_factory(data_len)
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elif subtable.type == ACPI_RTCT_V2_TYPE_MemoryHierarchyLatency:
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cls = RTCTSubtableMemoryHierarchyLatency_v2_factory(data_len)
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elif subtable.type == ACPI_RTCT_V2_TYPE_ErrorLogAddress:
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cls = RTCTSubtableErrorLogAddress
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else:
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cls = RTCTSubtableUnknown_factory(data_len)
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addr += subtable.subtable_size
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field_list.append( ('subtable{}'.format(subtable_num), cls) )
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return field_list
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def rtct_version_and_subtable_list(addr, length):
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version = rtct_version(addr, length)
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if version == 1:
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return (version, rtct_v1_subtable_list(addr, length))
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else:
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return (version, rtct_v2_subtable_list(addr, length))
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def rtct_factory(field_list, version):
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class subtables(cdata.Struct):
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_pack_ = 1
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_fields_ = field_list
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def __iter__(self):
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for f in self._fields_:
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yield getattr(self, f[0])
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class RTCT(cdata.Struct):
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_pack_ = 1
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_fields_ = [
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('header', TableHeader),
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('entries', subtables),
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]
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@property
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def version(self):
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return version
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return RTCT
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def RTCT(val):
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"""Create class based on decode of an RTCT table from filename."""
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base_length = ctypes.sizeof(rtct_factory(list(), 0))
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data = open(val, mode='rb').read()
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buf = ctypes.create_string_buffer(data, len(data))
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addr = ctypes.addressof(buf)
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hdr = TableHeader.from_address(addr)
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version, field_list = rtct_version_and_subtable_list(addr + base_length, hdr.length - base_length)
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return rtct_factory(field_list, version).from_buffer_copy(data)
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