Li, Fei1 4557033a3a hv: vlapic: minor fix about vlapic write ...

1) In x2apic mode, when read ICR, we want to read a 64-bits value.
2) In x2apic mode, write self-IPI will trap out through MSR write when VID isn't enabled.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>

2019-04-12 10:11:10 +08:00

60 KiB

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