mirror of
https://github.com/projectacrn/acrn-hypervisor.git
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9aa9a77457
Before this patch, guest temporary page tables were generated by hardcode at compile time, HV will copy this page tables to guest before guest launch. This patch creates temporary page tables at runtime for the range of 0~4G, and create page tables to cover new range(511G~511G+16M) with trusty requirement. Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com> Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
166 lines
4.9 KiB
ArmAsm
166 lines
4.9 KiB
ArmAsm
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <hypervisor.h>
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#include <spinlock.h>
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#include <gdt.h>
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#include <cpu.h>
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#include <mmu.h>
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#include <msr.h>
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.extern cpu_secondary_init
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.extern cpu_logical_id
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.extern _ld_bss_end
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.extern HOST_GDTR
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.section .cpu_secondary_reset,"ax"
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.align 4
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.code16
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.global cpu_secondary_reset
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cpu_secondary_reset:
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/* Disable local interrupts */
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cli
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/* Set DE, PAE, MCE and OS support bits in CR4 */
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movl $(CR4_DE | CR4_PAE | CR4_MCE | CR4_OSFXSR | CR4_OSXMMEXCPT), %eax
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mov %eax, %cr4
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/* Set CR3 to PML4 table address */
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movl $CPU_Boot_Page_Tables_Start, %edi
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mov %edi, %cr3
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/* Set LME bit in EFER */
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movl $MSR_IA32_EFER, %ecx
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rdmsr
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orl $MSR_IA32_EFER_LME_BIT, %eax
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wrmsr
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/* Enable paging, protection, numeric error and co-processor
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monitoring in CR0 to enter long mode */
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mov %cr0, %ebx
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orl $(CR0_PG | CR0_PE | CR0_MP | CR0_NE), %ebx
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mov %ebx, %cr0
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/* Load temportary GDT pointer value */
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mov $cpu_secondary_gdt_ptr, %ebx
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lgdt (%ebx)
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/* Perform a long jump based to start executing in 64-bit mode */
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data32 ljmp $HOST_GDT_RING0_CODE_SEL, $cpu_secondary_long_mode
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.code64
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cpu_secondary_long_mode:
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/* Set up all other data segment registers */
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movl $HOST_GDT_RING0_DATA_SEL, %eax
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mov %eax, %ss
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mov %eax, %ds
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mov %eax, %es
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mov %eax, %fs
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mov %eax, %gs
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/* Obtain secondary CPU spin-lock to serialize
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booting of secondary cores for a bit */
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spinlock_obtain(cpu_secondary_spinlock)
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/* Initialize temporary stack pointer
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NOTE: Using the PML4 memory (PDPT address is top of memory
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for the PML4 page) for the temporary stack
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as we are only using the very first entry in
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this page and the stack is growing down from
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the top of this page. This stack is only
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used for a VERY short period of time, so
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this reuse of PML4 memory should be acceptable. */
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movq $cpu_secondary_pdpt_addr, %rsp
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/* Push sp magic to top of stack for call trace */
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pushq $SP_BOTTOM_MAGIC
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/* Jump to C entry for the AP */
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call cpu_secondary_init
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cpu_secondary_error:
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/* Error condition trap */
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jmp cpu_secondary_error
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/* GDT table */
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.align 4
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cpu_secondary_gdt:
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.quad 0x0000000000000000
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.quad 0x00af9b000000ffff
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.quad 0x00cf93000000ffff
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cpu_secondary_gdt_end:
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/* GDT pointer */
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.align 2
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cpu_secondary_gdt_ptr:
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.short (cpu_secondary_gdt_end - cpu_secondary_gdt) - 1
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.quad cpu_secondary_gdt
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/* PML4, PDPT, and PD tables initialized to map first 4 GBytes of memory */
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.align CPU_PAGE_SIZE
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.global CPU_Boot_Page_Tables_Start
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CPU_Boot_Page_Tables_Start:
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.quad cpu_secondary_pdpt_addr + (IA32E_COMM_P_BIT | IA32E_COMM_RW_BIT)
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.align CPU_PAGE_SIZE
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cpu_secondary_pdpt_addr:
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address = 0
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.rept 4
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.quad cpu_secondary_pdt_addr + address + \
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(IA32E_COMM_P_BIT | IA32E_COMM_RW_BIT)
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address = address + CPU_PAGE_SIZE
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.endr
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.align CPU_PAGE_SIZE
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cpu_secondary_pdt_addr:
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address = 0
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.rept 2048
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.quad address + (IA32E_PDPTE_PS_BIT | IA32E_COMM_P_BIT | IA32E_COMM_RW_BIT)
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address = address + 0x200000
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.endr
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.end
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