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https://github.com/projectacrn/acrn-hypervisor.git
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85217e362f
As ACRN prepares to support platforms with multiple IO-APICs, GSI is a better way to represent physical and virtual INTx interrupt source. 1) This patch replaces usage of "pin" with "gsi" whereever applicable across the modules. 2) PIC pin to gsi is trickier and needs to consider the usage of "Interrupt Source Override" structure in ACPI for the corresponding VM. Tracked-On: #4151 Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com> Acked-by: Eddie Dong <eddie.dong@Intel.com>
192 lines
5.7 KiB
C
192 lines
5.7 KiB
C
/*-
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* Copyright (c) 2014 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com>
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* Copyright (c) 2017 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef VPIC_H
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#define VPIC_H
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/**
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* @file vpic.h
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*
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* @brief public APIs for virtual PIC
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*/
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#define ICU_IMR_OFFSET 1U
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/* Initialization control word 1. Written to even address. */
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#define ICW1_IC4 0x01U /* ICW4 present */
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#define ICW1_SNGL 0x02U /* 1 = single, 0 = cascaded */
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#define ICW1_ADI 0x04U /* 1 = 4, 0 = 8 byte vectors */
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#define ICW1_LTIM 0x08U /* 1 = level trigger, 0 = edge */
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#define ICW1_RESET 0x10U /* must be 1 */
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/* 0x20 - 0x80 - in 8080/8085 mode only */
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/* Initialization control word 2. Written to the odd address. */
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/* No definitions, it is the base vector of the IDT for 8086 mode */
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/* Initialization control word 3. Written to the odd address. */
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/* For a master PIC, bitfield indicating a slave 8259 on given input */
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/* For slave, lower 3 bits are the slave's ID binary id on master */
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/* Initialization control word 4. Written to the odd address. */
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#define ICW4_8086 0x01U /* 1 = 8086, 0 = 8080 */
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#define ICW4_AEOI 0x02U /* 1 = Auto EOI */
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#define ICW4_MS 0x04U /* 1 = buffered master, 0 = slave */
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#define ICW4_BUF 0x08U /* 1 = enable buffer mode */
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#define ICW4_SFNM 0x10U /* 1 = special fully nested mode */
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/* Operation control words. Written after initialization. */
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/* Operation control word type 1 */
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/*
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* No definitions. Written to the odd address. Bitmask for interrupts.
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* 1 = disabled.
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*/
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/* Operation control word type 2. Bit 3 (0x08) must be zero. Even address. */
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#define OCW2_L0 0x01U /* Level */
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#define OCW2_L1 0x02U
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#define OCW2_L2 0x04U
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/* 0x08 must be 0 to select OCW2 vs OCW3 */
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/* 0x10 must be 0 to select OCW2 vs ICW1 */
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#define OCW2_EOI 0x20U /* 1 = EOI */
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#define OCW2_SL 0x40U /* EOI mode */
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#define OCW2_R 0x80U /* EOI mode */
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/* Operation control word type 3. Bit 3 (0x08) must be set. Even address. */
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#define OCW3_RIS 0x01U /* 1 = read IS, 0 = read IR */
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#define OCW3_RR 0x02U /* register read */
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#define OCW3_P 0x04U /* poll mode command */
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/* 0x08 must be 1 to select OCW3 vs OCW2 */
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#define OCW3_SEL 0x08U /* must be 1 */
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/* 0x10 must be 0 to select OCW3 vs ICW1 */
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#define OCW3_SMM 0x20U /* special mode mask */
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#define OCW3_ESMM 0x40U /* enable SMM */
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#define IO_ELCR1 0x4d0U
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#define IO_ELCR2 0x4d1U
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#define NR_VPIC_PINS_PER_CHIP 8U
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#define NR_VPIC_PINS_TOTAL 16U
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enum vpic_wire_mode {
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VPIC_WIRE_INTR = 0,
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VPIC_WIRE_LAPIC,
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VPIC_WIRE_IOAPIC,
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VPIC_WIRE_NULL
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};
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enum vpic_trigger {
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EDGE_TRIGGER,
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LEVEL_TRIGGER
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};
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struct i8259_reg_state {
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bool ready;
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uint8_t icw_num;
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uint8_t rd_cmd_reg;
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bool aeoi;
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bool poll;
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bool rotate;
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bool sfn; /* special fully-nested mode */
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uint32_t irq_base;
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uint8_t request; /* Interrupt Request Register (IIR) */
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uint8_t service; /* Interrupt Service (ISR) */
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uint8_t mask; /* Interrupt Mask Register (IMR) */
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uint8_t smm; /* special mask mode */
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uint8_t pin_state[8]; /* pin state for level */
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uint32_t lowprio; /* lowest priority irq */
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bool intr_raised;
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uint8_t elc;
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};
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struct acrn_vpic {
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struct acrn_vm *vm;
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spinlock_t lock;
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struct i8259_reg_state i8259[2];
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};
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void vpic_init(struct acrn_vm *vm);
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/**
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* @brief virtual PIC
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*
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* @addtogroup acrn_vpic ACRN vPIC
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* @{
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*/
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/**
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* @brief Set vPIC IRQ line status.
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*
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* @param[in] vpic Pointer to target VM's vpic table
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* @param[in] vgsi GSI for the virtual interrupt
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* @param[in] operation action options:GSI_SET_HIGH/GSI_SET_LOW/
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* GSI_RAISING_PULSE/GSI_FALLING_PULSE
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*
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* @return None
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*/
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void vpic_set_irqline(struct acrn_vpic *vpic, uint32_t vgsi, uint32_t operation);
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/**
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* @brief Get pending virtual interrupts for vPIC.
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*
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* @param[in] vpic Pointer to target VM's vpic table
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* @param[inout] vecptr Pointer to vector buffer and will be filled
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* with eligible vector if any.
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*
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* @return None
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*/
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void vpic_pending_intr(struct acrn_vpic *vpic, uint32_t *vecptr);
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/**
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* @brief Accept virtual interrupt for vPIC.
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*
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* @param[in] vpic Pointer to target VM's vpic table
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* @param[in] vector Target virtual interrupt vector
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*
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* @return None
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*
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* @pre vm != NULL
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*/
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void vpic_intr_accepted(struct acrn_vpic *vpic, uint32_t vector);
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void vpic_get_irqline_trigger_mode(const struct acrn_vpic *vpic, uint32_t vgsi, enum vpic_trigger *trigger);
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uint32_t vpic_pincount(void);
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struct acrn_vpic *vm_pic(const struct acrn_vm *vm);
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/**
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* @}
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*/
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/* End of acrn_vpic */
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#endif /* VPIC_H */
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