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Merge "Makes UART driver never read FIFO_STATUS.RXLVL"

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GitOrigin-RevId: 3ccf8d334a7e73c5647a9733cde9d2cea94c568a
This commit is contained in:
Matt Harvey 2021-10-06 01:12:19 +00:00 committed by Sam Leffler
parent 61fbe78415
commit 6f942b860a
1 changed files with 5 additions and 7 deletions
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12
apps/system/components/OpenTitanUARTDriver/src/driver.c
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@ -67,12 +67,10 @@ static uint32_t tx_fifo_level() {
return SHIFT_DOWN_AND_MASK(REG(FIFO_STATUS), FIFO_STATUS, TXLVL);
}
// Gets the number of pending bytes in the RX FIFO from hardware MMIO.
static uint32_t rx_fifo_level() {
return SHIFT_DOWN_AND_MASK(REG(FIFO_STATUS), FIFO_STATUS, RXLVL);
}
// Gets whether the receive FIFO empty status bit is set.
//
// Prefer this to FIFO_STATUS.RXLVL, which the simulation has sometimes reported
// as zero even when "not STATUS.RXEMPTY."
static bool rx_empty() {
return REG(STATUS) & (1 << UART_STATUS_RXEMPTY);
}
@ -269,7 +267,7 @@ void tx_watermark_handle(void) {
// be waiting on the condition that rx_buf not be empty.
void rx_watermark_handle(void) {
LOCK(rx_mutex);
while (rx_fifo_level() > 0 || !rx_empty()) {
while (!rx_empty()) {
if (!circular_buffer_push_back(&rx_buf, uart_getchar())) {
// The buffer is full.
break;
@ -280,7 +278,7 @@ void rx_watermark_handle(void) {
}
UNLOCK(rx_mutex);
if (rx_fifo_level() == 0 && rx_empty()) {
if (rx_empty()) {
// Clears INTR_STATE for rx_watermark. (INTR_STATE is write-1-to-clear.)
REG(INTR_STATE) = BIT(UART_INTR_STATE_RX_WATERMARK);
seL4_Assert(rx_watermark_acknowledge() == 0);