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Enables UART tx_watermark interrupts

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With Renode at HEAD, this causes an infinite loop. It seems like the
Renode OpenTitan UART does not have "edge triggered" behavior.

Change-Id: Ic553ce34cabaf8287c7969904d6336d1acf339a0
GitOrigin-RevId: 010f0d7045d40ea6b0900fc74d79fe92df0fae69
This commit is contained in:
Matt Harvey 2021-08-19 19:36:37 -07:00 committed by Sam Leffler
parent b7727a0823
commit b35f77a2fe
1 changed files with 1 additions and 9 deletions
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10
apps/system/components/OpenTitanUARTDriver/src/driver.c
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@ -163,12 +163,7 @@ void pre_init() {
// Enables interrupts. // Enables interrupts.
REG(INTR_ENABLE) = ( REG(INTR_ENABLE) = (
// TODO(mattharvey): Enable tx_watermark. Currently the handler fires BIT(UART_INTR_COMMON_TX_WATERMARK) |
// repeatedly in a loop when doing this, even while the TX FIFO remains
// empty, contrary to the "edge triggered events" working in the OpenTitan
// docs. Check that Renode is doing the right thing and if so debug after
// re-enabling this.
// BIT(UART_INTR_COMMON_TX_WATERMARK) |
BIT(UART_INTR_COMMON_RX_WATERMARK) | BIT(UART_INTR_COMMON_TX_EMPTY)); BIT(UART_INTR_COMMON_RX_WATERMARK) | BIT(UART_INTR_COMMON_TX_EMPTY));
} }
@ -239,9 +234,6 @@ void tx_update(uint32_t num_valid_dataport_bytes) {
// These happen when the transmit FIFO is half-empty. This refills the FIFO to // These happen when the transmit FIFO is half-empty. This refills the FIFO to
// prevent stalling, stopping early if tx_buf becomes empty, and then signals // prevent stalling, stopping early if tx_buf becomes empty, and then signals
// any tx_update that might be waiting for tx_buf to not be full. // any tx_update that might be waiting for tx_buf to not be full.
//
// Currently this is not actually enabled. See the TODO in the implementation of
// pre_init.
void tx_watermark_handle(void) { void tx_watermark_handle(void) {
fill_tx_fifo(); fill_tx_fifo();