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hv: riscv: add arch_asm_pause implementation

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Extension Zihintpause (Pause hint) is mandatory for RVA23. asm_pause
is implemented based on "pause" instruction.

Tracked-On: #8791
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
This commit is contained in:
Jian Jun Chen
2025-09-10 15:42:47 +08:00
committed by acrnsi-robot
parent 8d218c0b37
commit 0e6e6ca502
2 changed files with 6 additions and 0 deletions
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1
hypervisor/arch/riscv/Makefile
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@@ -19,6 +19,7 @@ LDFLAGS += -Wl,--no-warn-rwx-segments
RV_ISA += gh
RV_ISA += zbb
RV_ISA += zicbom
RV_ISA += zihintpause
ARCH_CFLAGS += -march=rv64$(subst $() $(),_,$(RV_ISA))
ARCH_CFLAGS += -mabi=lp64d

5
hypervisor/include/arch/riscv/asm/cpu.h
View File

@@ -46,6 +46,11 @@ static inline void arch_set_current_pcpu_id(uint16_t pcpu_id)
asm volatile ("mv tp, %0" : : "r" (pcpu_id) : "tp");
}
static inline void arch_asm_pause(void)
{
asm volatile ("pause" ::: "memory");
}
/* Write CSR */
#define cpu_csr_write(reg, csr_val) \
({ \