mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-06-25 23:13:26 +00:00
HV:CPU: Add 'U/UL' for unsigned const value
According to MISRA C:2012, suffix 'U/UL' shall be for
unsigned const value, the member of enum variable should
not be used to compare with integer variable.
Add 'U/UL' for unsigned const value in the CPU module;
Use Macro insteading of enum feature_word since the member
of feature_word is used to compare with integer variable;
Use hex number insteading of Macro in the assembly code.
V1-->V2:
Update the suffix of some constant value as 'UL'
according to its'storage variable;
Split MACRO updates used in the assembly code
in other patch.
Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Xiangyang Wu
wenlingz
parent
21f0bddff8
commit
474e9af216
@ -28,7 +28,7 @@ uint64_t pcpu_sync = 0UL;
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volatile uint16_t up_count = 0U;
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/* physical cpu active bitmap, support up to 64 cpus */
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uint64_t pcpu_active_bitmap = 0;
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uint64_t pcpu_active_bitmap = 0UL;
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uint64_t trampoline_start16_paddr;
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@ -77,7 +77,7 @@ inline bool cpu_has_cap(uint32_t bit)
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if (feat_idx >= FEATURE_WORDS)
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return false;
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return ((boot_cpu_data.cpuid_leaves[feat_idx] & (1 << feat_bit)) != 0U);
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return ((boot_cpu_data.cpuid_leaves[feat_idx] & (1U << feat_bit)) != 0U);
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}
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static inline bool get_monitor_cap(void)
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@ -111,15 +111,15 @@ static void get_cpu_capabilities(void)
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cpuid(CPUID_FEATURES, &eax, &unused,
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&boot_cpu_data.cpuid_leaves[FEAT_1_ECX],
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&boot_cpu_data.cpuid_leaves[FEAT_1_EDX]);
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family = (eax >> 8) & 0xffU;
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family = (eax >> 8U) & 0xffU;
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if (family == 0xFU)
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family += (eax >> 20) & 0xffU;
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family += (eax >> 20U) & 0xffU;
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boot_cpu_data.x86 = family;
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model = (eax >> 4) & 0xfU;
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model = (eax >> 4U) & 0xfU;
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if (family >= 0x06U)
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model += ((eax >> 16) & 0xfU) << 4;
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boot_cpu_data.x86_model = model;
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model += ((eax >> 16U) & 0xfU) << 4U;
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boot_cpu_data.x86_model = (uint8_t)model;
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cpuid(CPUID_EXTEND_FEATURE, &unused,
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@ -144,8 +144,8 @@ static void get_cpu_capabilities(void)
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/* EAX bits 07-00: #Physical Address Bits
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* bits 15-08: #Linear Address Bits
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*/
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boot_cpu_data.x86_virt_bits = (eax >> 8) & 0xffU;
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boot_cpu_data.x86_phys_bits = eax & 0xffU;
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boot_cpu_data.x86_virt_bits = (uint8_t)((eax >> 8U) & 0xffU);
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boot_cpu_data.x86_phys_bits = (uint8_t)(eax & 0xffU);
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boot_cpu_data.physical_address_mask =
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get_address_mask(boot_cpu_data.x86_phys_bits);
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}
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@ -317,7 +317,7 @@ static void cpu_set_current_state(uint16_t pcpu_id, enum cpu_state state)
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#ifdef STACK_PROTECTOR
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static uint64_t get_random_value(void)
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{
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uint64_t random = 0;
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uint64_t random = 0UL;
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asm volatile ("1: rdrand %%rax\n"
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"jnc 1b\n"
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@ -374,7 +374,7 @@ void bsp_boot_init(void)
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* is matching the actual offset!
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*/
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ASSERT(sizeof(struct trusty_startup_param)
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+ sizeof(struct key_info) < 0x1000,
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+ sizeof(struct key_info) < 0x1000U,
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"trusty_startup_param + key_info > 1Page size(4KB)!");
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ASSERT(NR_WORLD == 2, "Only 2 Worlds supported!");
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@ -507,7 +507,7 @@ static void bsp_boot_post(void)
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pr_acrnlog("Detect processor: %s", boot_cpu_data.model_name);
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pr_dbg("Core %d is up", CPU_BOOT_ID);
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pr_dbg("Core %hu is up", CPU_BOOT_ID);
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if (hardware_detect_support() != 0) {
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pr_fatal("hardware not support!\n");
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@ -606,7 +606,7 @@ static void cpu_secondary_post(void)
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/* Make sure rdtsc is enabled */
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check_tsc();
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pr_dbg("Core %d is up", get_cpu_id());
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pr_dbg("Core %hu is up", get_cpu_id());
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cpu_xsave_init();
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@ -616,7 +616,7 @@ static void cpu_secondary_post(void)
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timer_init();
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/* Wait for boot processor to signal all secondary cores to continue */
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pcpu_sync_sleep(&pcpu_sync, 0);
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pcpu_sync_sleep(&pcpu_sync, 0UL);
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ret = hv_main(get_cpu_id());
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if (ret != 0)
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@ -728,10 +728,10 @@ void start_cpus()
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timeout = CONFIG_CPU_UP_TIMEOUT * 1000;
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while ((up_count != expected_up) && (timeout != 0U)) {
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/* Delay 10us */
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udelay(10);
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udelay(10U);
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/* Decrement timeout value */
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timeout -= 10;
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timeout -= 10U;
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}
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/* Check to see if all expected CPUs are actually up */
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@ -761,10 +761,10 @@ void stop_cpus()
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expected_up = 1U;
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while ((up_count != expected_up) && (timeout != 0U)) {
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/* Delay 10us */
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udelay(10);
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udelay(10U);
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/* Decrement timeout value */
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timeout -= 10;
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timeout -= 10U;
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}
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if (up_count != expected_up) {
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@ -864,7 +864,7 @@ static bool is_ctrl_setting_allowed(uint64_t msr_val, uint32_t ctrl)
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* - bitX in ctrl can be set 1
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* only if bit 32+X in msr_val is 1
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*/
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return ((((uint32_t)(msr_val >> 32)) & ctrl) == ctrl);
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return ((((uint32_t)(msr_val >> 32UL)) & ctrl) == ctrl);
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}
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static void vapic_cap_detect(void)
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@ -908,17 +908,17 @@ static void vapic_cap_detect(void)
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bool is_vapic_supported(void)
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{
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return ((cpu_caps.vapic_features & VAPIC_FEATURE_VIRT_ACCESS) != 0);
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return ((cpu_caps.vapic_features & VAPIC_FEATURE_VIRT_ACCESS) != 0U);
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}
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bool is_vapic_intr_delivery_supported(void)
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{
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return ((cpu_caps.vapic_features & VAPIC_FEATURE_INTR_DELIVERY) != 0);
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return ((cpu_caps.vapic_features & VAPIC_FEATURE_INTR_DELIVERY) != 0U);
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}
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bool is_vapic_virt_reg_supported(void)
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{
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return ((cpu_caps.vapic_features & VAPIC_FEATURE_VIRT_REG) != 0);
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return ((cpu_caps.vapic_features & VAPIC_FEATURE_VIRT_REG) != 0U);
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}
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static void cpu_xsave_init(void)
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@ -8,67 +8,67 @@
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/* The table includes cpu px info of Intel A3960 SoC */
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static const struct cpu_px_data px_a3960[] = {
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{0x960, 0, 0xA, 0xA, 0x1800, 0x1800}, /* P0 */
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{0x8FC, 0, 0xA, 0xA, 0x1700, 0x1700}, /* P1 */
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{0x898, 0, 0xA, 0xA, 0x1600, 0x1600}, /* P2 */
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{0x834, 0, 0xA, 0xA, 0x1500, 0x1500}, /* P3 */
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{0x7D0, 0, 0xA, 0xA, 0x1400, 0x1400}, /* P4 */
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{0x76C, 0, 0xA, 0xA, 0x1300, 0x1300}, /* P5 */
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{0x708, 0, 0xA, 0xA, 0x1200, 0x1200}, /* P6 */
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{0x6A4, 0, 0xA, 0xA, 0x1100, 0x1100}, /* P7 */
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{0x640, 0, 0xA, 0xA, 0x1000, 0x1000}, /* P8 */
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{0x5DC, 0, 0xA, 0xA, 0x0F00, 0x0F00}, /* P9 */
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{0x578, 0, 0xA, 0xA, 0x0E00, 0x0E00}, /* P10 */
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{0x514, 0, 0xA, 0xA, 0x0D00, 0x0D00}, /* P11 */
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{0x4B0, 0, 0xA, 0xA, 0x0C00, 0x0C00}, /* P12 */
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{0x44C, 0, 0xA, 0xA, 0x0B00, 0x0B00}, /* P13 */
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{0x3E8, 0, 0xA, 0xA, 0x0A00, 0x0A00}, /* P14 */
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{0x384, 0, 0xA, 0xA, 0x0900, 0x0900}, /* P15 */
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{0x320, 0, 0xA, 0xA, 0x0800, 0x0800} /* P16 */
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{0x960UL, 0UL, 0xAUL, 0xAUL, 0x1800UL, 0x1800UL}, /* P0 */
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{0x8FCUL, 0UL, 0xAUL, 0xAUL, 0x1700UL, 0x1700UL}, /* P1 */
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{0x898UL, 0UL, 0xAUL, 0xAUL, 0x1600UL, 0x1600UL}, /* P2 */
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{0x834UL, 0UL, 0xAUL, 0xAUL, 0x1500UL, 0x1500UL}, /* P3 */
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{0x7D0UL, 0UL, 0xAUL, 0xAUL, 0x1400UL, 0x1400UL}, /* P4 */
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{0x76CUL, 0UL, 0xAUL, 0xAUL, 0x1300UL, 0x1300UL}, /* P5 */
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{0x708UL, 0UL, 0xAUL, 0xAUL, 0x1200UL, 0x1200UL}, /* P6 */
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{0x6A4UL, 0UL, 0xAUL, 0xAUL, 0x1100UL, 0x1100UL}, /* P7 */
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{0x640UL, 0UL, 0xAUL, 0xAUL, 0x1000UL, 0x1000UL}, /* P8 */
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{0x5DCUL, 0UL, 0xAUL, 0xAUL, 0x0F00UL, 0x0F00UL}, /* P9 */
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{0x578UL, 0UL, 0xAUL, 0xAUL, 0x0E00UL, 0x0E00UL}, /* P10 */
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{0x514UL, 0UL, 0xAUL, 0xAUL, 0x0D00UL, 0x0D00UL}, /* P11 */
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{0x4B0UL, 0UL, 0xAUL, 0xAUL, 0x0C00UL, 0x0C00UL}, /* P12 */
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{0x44CUL, 0UL, 0xAUL, 0xAUL, 0x0B00UL, 0x0B00UL}, /* P13 */
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{0x3E8UL, 0UL, 0xAUL, 0xAUL, 0x0A00UL, 0x0A00UL}, /* P14 */
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{0x384UL, 0UL, 0xAUL, 0xAUL, 0x0900UL, 0x0900UL}, /* P15 */
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{0x320UL, 0UL, 0xAUL, 0xAUL, 0x0800UL, 0x0800UL} /* P16 */
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};
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/* The table includes cpu cx info of Intel A3960 SoC */
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static const struct cpu_cx_data cx_a3960[] = {
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{{SPACE_FFixedHW, 0x0, 0, 0, 0}, 0x1, 0x1, 0x3E8}, /* C1 */
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{{SPACE_SYSTEM_IO, 0x8, 0, 0, 0x415}, 0x2, 0x32, 0x0A}, /* C2 */
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{{SPACE_SYSTEM_IO, 0x8, 0, 0, 0x419}, 0x3, 0x96, 0x0A} /* C3 */
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{{SPACE_FFixedHW, 0x0U, 0U, 0U, 0UL}, 0x1U, 0x1U, 0x3E8UL}, /* C1 */
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{{SPACE_SYSTEM_IO, 0x8U, 0U, 0U, 0x415UL}, 0x2U, 0x32U, 0x0AUL}, /* C2 */
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{{SPACE_SYSTEM_IO, 0x8U, 0U, 0U, 0x419UL}, 0x3U, 0x96U, 0x0AUL} /* C3 */
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};
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/* The table includes cpu px info of Intel A3950 SoC */
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static const struct cpu_px_data px_a3950[] = {
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{0x7D0, 0, 0xA, 0xA, 0x1400, 0x1400}, /* P0 */
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{0x76C, 0, 0xA, 0xA, 0x1300, 0x1300}, /* P1 */
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{0x708, 0, 0xA, 0xA, 0x1200, 0x1200}, /* P2 */
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{0x6A4, 0, 0xA, 0xA, 0x1100, 0x1100}, /* P3 */
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{0x640, 0, 0xA, 0xA, 0x1000, 0x1000}, /* P4 */
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{0x5DC, 0, 0xA, 0xA, 0x0F00, 0x0F00}, /* P5 */
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{0x578, 0, 0xA, 0xA, 0x0E00, 0x0E00}, /* P6 */
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{0x514, 0, 0xA, 0xA, 0x0D00, 0x0D00}, /* P7 */
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{0x4B0, 0, 0xA, 0xA, 0x0C00, 0x0C00}, /* P8 */
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{0x44C, 0, 0xA, 0xA, 0x0B00, 0x0B00}, /* P9 */
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{0x3E8, 0, 0xA, 0xA, 0x0A00, 0x0A00}, /* P10 */
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{0x384, 0, 0xA, 0xA, 0x0900, 0x0900}, /* P11 */
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{0x320, 0, 0xA, 0xA, 0x0800, 0x0800} /* P12 */
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{0x7D0UL, 0UL, 0xAUL, 0xAUL, 0x1400UL, 0x1400UL}, /* P0 */
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{0x76CUL, 0UL, 0xAUL, 0xAUL, 0x1300UL, 0x1300UL}, /* P1 */
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{0x708UL, 0UL, 0xAUL, 0xAUL, 0x1200UL, 0x1200UL}, /* P2 */
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{0x6A4UL, 0UL, 0xAUL, 0xAUL, 0x1100UL, 0x1100UL}, /* P3 */
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{0x640UL, 0UL, 0xAUL, 0xAUL, 0x1000UL, 0x1000UL}, /* P4 */
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{0x5DCUL, 0UL, 0xAUL, 0xAUL, 0x0F00UL, 0x0F00UL}, /* P5 */
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{0x578UL, 0UL, 0xAUL, 0xAUL, 0x0E00UL, 0x0E00UL}, /* P6 */
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{0x514UL, 0UL, 0xAUL, 0xAUL, 0x0D00UL, 0x0D00UL}, /* P7 */
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{0x4B0UL, 0UL, 0xAUL, 0xAUL, 0x0C00UL, 0x0C00UL}, /* P8 */
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{0x44CUL, 0UL, 0xAUL, 0xAUL, 0x0B00UL, 0x0B00UL}, /* P9 */
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{0x3E8UL, 0UL, 0xAUL, 0xAUL, 0x0A00UL, 0x0A00UL}, /* P10 */
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{0x384UL, 0UL, 0xAUL, 0xAUL, 0x0900UL, 0x0900UL}, /* P11 */
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{0x320UL, 0UL, 0xAUL, 0xAUL, 0x0800UL, 0x0800UL} /* P12 */
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};
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/* The table includes cpu px info of Intel J3455 SoC */
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static const struct cpu_px_data px_j3455[] = {
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{0x5DD, 0, 0xA, 0xA, 0x1700, 0x1700}, /* P0 */
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{0x5DC, 0, 0xA, 0xA, 0x0F00, 0x0F00}, /* P1 */
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{0x578, 0, 0xA, 0xA, 0x0E00, 0x0E00}, /* P2 */
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{0x514, 0, 0xA, 0xA, 0x0D00, 0x0D00}, /* P3 */
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{0x4B0, 0, 0xA, 0xA, 0x0C00, 0x0C00}, /* P4 */
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{0x44C, 0, 0xA, 0xA, 0x0B00, 0x0B00}, /* P5 */
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{0x3E8, 0, 0xA, 0xA, 0x0A00, 0x0A00}, /* P6 */
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{0x384, 0, 0xA, 0xA, 0x0900, 0x0900}, /* P7 */
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{0x320, 0, 0xA, 0xA, 0x0800, 0x0800} /* P8 */
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{0x5DDUL, 0UL, 0xAUL, 0xAUL, 0x1700UL, 0x1700UL}, /* P0 */
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{0x5DCUL, 0UL, 0xAUL, 0xAUL, 0x0F00UL, 0x0F00UL}, /* P1 */
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{0x578UL, 0UL, 0xAUL, 0xAUL, 0x0E00UL, 0x0E00UL}, /* P2 */
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{0x514UL, 0UL, 0xAUL, 0xAUL, 0x0D00UL, 0x0D00UL}, /* P3 */
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{0x4B0UL, 0UL, 0xAUL, 0xAUL, 0x0C00UL, 0x0C00UL}, /* P4 */
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{0x44CUL, 0UL, 0xAUL, 0xAUL, 0x0B00UL, 0x0B00UL}, /* P5 */
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{0x3E8UL, 0UL, 0xAUL, 0xAUL, 0x0A00UL, 0x0A00UL}, /* P6 */
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{0x384UL, 0UL, 0xAUL, 0xAUL, 0x0900UL, 0x0900UL}, /* P7 */
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{0x320UL, 0UL, 0xAUL, 0xAUL, 0x0800UL, 0x0800UL} /* P8 */
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};
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/* The table includes cpu cx info of Intel J3455 SoC */
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static const struct cpu_cx_data cx_j3455[] = {
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{{SPACE_FFixedHW, 0x1, 0x2, 0x1, 0x01}, 0x1, 0x1, 0x3E8}, /* C1 */
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{{SPACE_FFixedHW, 0x1, 0x2, 0x1, 0x21}, 0x2, 0x32, 0x0A}, /* C2 */
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{{SPACE_FFixedHW, 0x1, 0x2, 0x1, 0x60}, 0x3, 0x96, 0x0A} /* C3 */
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{{SPACE_FFixedHW, 0x1U, 0x2U, 0x1U, 0x01UL}, 0x1U, 0x1U, 0x3E8UL}, /* C1 */
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{{SPACE_FFixedHW, 0x1U, 0x2U, 0x1U, 0x21UL}, 0x2U, 0x32U, 0x0AUL}, /* C2 */
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{{SPACE_FFixedHW, 0x1U, 0x2U, 0x1U, 0x60UL}, 0x3U, 0x96U, 0x0AUL} /* C3 */
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};
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static const struct cpu_state_table {
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@ -113,7 +113,7 @@ void load_cpu_state_data(void)
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int tbl_idx;
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const struct cpu_state_info *state_info;
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(void)memset(&boot_cpu_data.state_info, 0,
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(void)memset(&boot_cpu_data.state_info, 0U,
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sizeof(struct cpu_state_info));
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tbl_idx = get_state_tbl_idx(boot_cpu_data.model_name);
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@ -36,7 +36,7 @@ static inline struct vcpuid_entry *find_vcpuid_entry(struct vcpu *vcpu,
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if (entry == NULL) {
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uint32_t limit;
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if ((leaf & 0x80000000) != 0U)
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if ((leaf & 0x80000000U) != 0U)
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limit = vm->vcpuid_xlevel;
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else
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limit = vm->vcpuid_level;
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@ -160,7 +160,7 @@ int set_vcpuid_entries(struct vm *vm)
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uint32_t limit;
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uint32_t i, j;
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init_vcpuid_entry(vm, 0, 0, 0, &entry);
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init_vcpuid_entry(vm, 0U, 0U, 0U, &entry);
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result = set_vcpuid_entry(vm, &entry);
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if (result != 0)
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return result;
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@ -176,7 +176,7 @@ int set_vcpuid_entries(struct vm *vm)
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{
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uint32_t times;
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init_vcpuid_entry(vm, i, 0,
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init_vcpuid_entry(vm, i, 0U,
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CPUID_CHECK_SUBLEAF, &entry);
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result = set_vcpuid_entry(vm, &entry);
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if (result != 0)
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@ -212,7 +212,7 @@ int set_vcpuid_entries(struct vm *vm)
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break;
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default:
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||||
init_vcpuid_entry(vm, i, 0, 0, &entry);
|
||||
init_vcpuid_entry(vm, i, 0U, 0U, &entry);
|
||||
result = set_vcpuid_entry(vm, &entry);
|
||||
if (result != 0)
|
||||
return result;
|
||||
@ -220,24 +220,24 @@ int set_vcpuid_entries(struct vm *vm)
|
||||
}
|
||||
}
|
||||
|
||||
init_vcpuid_entry(vm, 0x40000000, 0, 0, &entry);
|
||||
init_vcpuid_entry(vm, 0x40000000U, 0U, 0U, &entry);
|
||||
result = set_vcpuid_entry(vm, &entry);
|
||||
if (result != 0)
|
||||
return result;
|
||||
|
||||
init_vcpuid_entry(vm, 0x40000010, 0, 0, &entry);
|
||||
init_vcpuid_entry(vm, 0x40000010U, 0U, 0U, &entry);
|
||||
result = set_vcpuid_entry(vm, &entry);
|
||||
if (result != 0)
|
||||
return result;
|
||||
|
||||
init_vcpuid_entry(vm, 0x80000000, 0, 0, &entry);
|
||||
init_vcpuid_entry(vm, 0x80000000U, 0U, 0U, &entry);
|
||||
result = set_vcpuid_entry(vm, &entry);
|
||||
if (result != 0)
|
||||
return result;
|
||||
|
||||
vm->vcpuid_xlevel = limit = entry.eax;
|
||||
for (i = 0x80000001U; i <= limit; i++) {
|
||||
init_vcpuid_entry(vm, i, 0, 0, &entry);
|
||||
init_vcpuid_entry(vm, i, 0U, 0U, &entry);
|
||||
result = set_vcpuid_entry(vm, &entry);
|
||||
if (result != 0)
|
||||
return result;
|
||||
@ -309,7 +309,7 @@ void guest_cpuid(struct vcpu *vcpu,
|
||||
uint64_t cr4;
|
||||
/*read guest CR4*/
|
||||
cr4 = exec_vmread(VMX_GUEST_CR4);
|
||||
if ((cr4 & CR4_OSXSAVE) != 0U)
|
||||
if ((cr4 & CR4_OSXSAVE) != 0UL)
|
||||
*ecx |= CPUID_ECX_OSXSAVE;
|
||||
}
|
||||
break;
|
||||
|
||||
@ -52,7 +52,7 @@
|
||||
|
||||
#define MSR_IA32_PAT 0x00000277 /* PAT */
|
||||
#define MSR_IA32_EFER 0xC0000080
|
||||
#define MSR_IA32_FS_BASE 0xC0000100
|
||||
#define MSR_IA32_FS_BASE 0xC0000100U
|
||||
#define MSR_IA32_GS_BASE 0xC0000101
|
||||
#define MSR_IA32_SYSENTER_ESP 0x00000175 /* ESP for sysenter */
|
||||
#define MSR_IA32_SYSENTER_EIP 0x00000176 /* EIP for sysenter */
|
||||
|
||||
@ -67,25 +67,25 @@
|
||||
#define CR3_PCD (1U<<4) /* page-level cache disable */
|
||||
|
||||
/* CR4 register definitions */
|
||||
#define CR4_VME (1U<<0) /* virtual 8086 mode extensions */
|
||||
#define CR4_PVI (1U<<1) /* protected mode virtual interrupts */
|
||||
#define CR4_TSD (1U<<2) /* time stamp disable */
|
||||
#define CR4_DE (1U<<3) /* debugging extensions */
|
||||
#define CR4_PSE (1U<<4) /* page size extensions */
|
||||
#define CR4_PAE (1U<<5) /* physical address extensions */
|
||||
#define CR4_MCE (1U<<6) /* machine check enable */
|
||||
#define CR4_PGE (1U<<7) /* page global enable */
|
||||
#define CR4_PCE (1U<<8)
|
||||
#define CR4_VME (1UL<<0) /* virtual 8086 mode extensions */
|
||||
#define CR4_PVI (1UL<<1) /* protected mode virtual interrupts */
|
||||
#define CR4_TSD (1UL<<2) /* time stamp disable */
|
||||
#define CR4_DE (1UL<<3) /* debugging extensions */
|
||||
#define CR4_PSE (1UL<<4) /* page size extensions */
|
||||
#define CR4_PAE (1UL<<5) /* physical address extensions */
|
||||
#define CR4_MCE (1UL<<6) /* machine check enable */
|
||||
#define CR4_PGE (1UL<<7) /* page global enable */
|
||||
#define CR4_PCE (1UL<<8)
|
||||
/* performance monitoring counter enable */
|
||||
#define CR4_OSFXSR (1U<<9) /* OS support for FXSAVE/FXRSTOR */
|
||||
#define CR4_OSXMMEXCPT (1U<<10)
|
||||
#define CR4_OSFXSR (1UL<<9) /* OS support for FXSAVE/FXRSTOR */
|
||||
#define CR4_OSXMMEXCPT (1UL<<10)
|
||||
/* OS support for unmasked SIMD floating point exceptions */
|
||||
#define CR4_VMXE (1U<<13) /* VMX enable */
|
||||
#define CR4_SMXE (1U<<14) /* SMX enable */
|
||||
#define CR4_PCIDE (1U<<17) /* PCID enable */
|
||||
#define CR4_OSXSAVE (1U<<18)
|
||||
#define CR4_SMEP (1U<<20)
|
||||
#define CR4_SMAP (1U<<21)
|
||||
#define CR4_VMXE (1UL<<13) /* VMX enable */
|
||||
#define CR4_SMXE (1UL<<14) /* SMX enable */
|
||||
#define CR4_PCIDE (1UL<<17) /* PCID enable */
|
||||
#define CR4_OSXSAVE (1UL<<18)
|
||||
#define CR4_SMEP (1UL<<20)
|
||||
#define CR4_SMAP (1UL<<21)
|
||||
/* XSAVE and Processor Extended States enable bit */
|
||||
|
||||
|
||||
@ -197,18 +197,15 @@ extern spinlock_t trampoline_spinlock;
|
||||
((uint64_t)_ld_cpu_data_end - (uint64_t)(_ld_cpu_data_start))
|
||||
|
||||
/* CPUID feature words */
|
||||
enum feature_word {
|
||||
FEAT_1_ECX = 0, /* CPUID[1].ECX */
|
||||
FEAT_1_EDX, /* CPUID[1].EDX */
|
||||
FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */
|
||||
FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */
|
||||
FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */
|
||||
FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */
|
||||
FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */
|
||||
FEAT_8000_0008_EBX, /* CPUID[8000_0008].EAX */
|
||||
FEATURE_WORDS,
|
||||
};
|
||||
|
||||
#define FEAT_1_ECX 0U /* CPUID[1].ECX */
|
||||
#define FEAT_1_EDX 1U /* CPUID[1].EDX */
|
||||
#define FEAT_7_0_EBX 2U /* CPUID[EAX=7,ECX=0].EBX */
|
||||
#define FEAT_7_0_ECX 3U /* CPUID[EAX=7,ECX=0].ECX */
|
||||
#define FEAT_7_0_EDX 4U /* CPUID[EAX=7,ECX=0].EDX */
|
||||
#define FEAT_8000_0001_ECX 5U /* CPUID[8000_0001].ECX */
|
||||
#define FEAT_8000_0001_EDX 6U /* CPUID[8000_0001].EDX */
|
||||
#define FEAT_8000_0008_EBX 7U /* CPUID[8000_0008].EAX */
|
||||
#define FEATURE_WORDS 8U
|
||||
/**
|
||||
*The invalid cpu_id (INVALID_CPU_ID) is error
|
||||
*code for error handling, this means that
|
||||
|
||||
@ -8,79 +8,79 @@
|
||||
#define __X86_CPUFEATURES_H__
|
||||
|
||||
/* Intel-defined CPU features, CPUID level 0x00000001 (ECX)*/
|
||||
#define X86_FEATURE_SSE3 ((FEAT_1_ECX << 5) + 0)
|
||||
#define X86_FEATURE_PCLMUL ((FEAT_1_ECX << 5) + 1)
|
||||
#define X86_FEATURE_DTES64 ((FEAT_1_ECX << 5) + 2)
|
||||
#define X86_FEATURE_MONITOR ((FEAT_1_ECX << 5) + 3)
|
||||
#define X86_FEATURE_DS_CPL ((FEAT_1_ECX << 5) + 4)
|
||||
#define X86_FEATURE_VMX ((FEAT_1_ECX << 5) + 5)
|
||||
#define X86_FEATURE_SMX ((FEAT_1_ECX << 5) + 6)
|
||||
#define X86_FEATURE_EST ((FEAT_1_ECX << 5) + 7)
|
||||
#define X86_FEATURE_TM2 ((FEAT_1_ECX << 5) + 8)
|
||||
#define X86_FEATURE_SSSE3 ((FEAT_1_ECX << 5) + 9)
|
||||
#define X86_FEATURE_CID ((FEAT_1_ECX << 5) + 10)
|
||||
#define X86_FEATURE_FMA ((FEAT_1_ECX << 5) + 12)
|
||||
#define X86_FEATURE_CX16 ((FEAT_1_ECX << 5) + 13)
|
||||
#define X86_FEATURE_ETPRD ((FEAT_1_ECX << 5) + 14)
|
||||
#define X86_FEATURE_PDCM ((FEAT_1_ECX << 5) + 15)
|
||||
#define X86_FEATURE_PCID ((FEAT_1_ECX << 5) + 17)
|
||||
#define X86_FEATURE_DCA ((FEAT_1_ECX << 5) + 18)
|
||||
#define X86_FEATURE_SSE4_1 ((FEAT_1_ECX << 5) + 19)
|
||||
#define X86_FEATURE_SSE4_2 ((FEAT_1_ECX << 5) + 20)
|
||||
#define X86_FEATURE_x2APIC ((FEAT_1_ECX << 5) + 21)
|
||||
#define X86_FEATURE_MOVBE ((FEAT_1_ECX << 5) + 22)
|
||||
#define X86_FEATURE_POPCNT ((FEAT_1_ECX << 5) + 23)
|
||||
#define X86_FEATURE_TSC_DEADLINE ((FEAT_1_ECX << 5) + 24)
|
||||
#define X86_FEATURE_AES ((FEAT_1_ECX << 5) + 25)
|
||||
#define X86_FEATURE_XSAVE ((FEAT_1_ECX << 5) + 26)
|
||||
#define X86_FEATURE_OSXSAVE ((FEAT_1_ECX << 5) + 27)
|
||||
#define X86_FEATURE_AVX ((FEAT_1_ECX << 5) + 28)
|
||||
#define X86_FEATURE_SSE3 ((FEAT_1_ECX << 5U) + 0U)
|
||||
#define X86_FEATURE_PCLMUL ((FEAT_1_ECX << 5U) + 1U)
|
||||
#define X86_FEATURE_DTES64 ((FEAT_1_ECX << 5U) + 2U)
|
||||
#define X86_FEATURE_MONITOR ((FEAT_1_ECX << 5U) + 3U)
|
||||
#define X86_FEATURE_DS_CPL ((FEAT_1_ECX << 5U) + 4U)
|
||||
#define X86_FEATURE_VMX ((FEAT_1_ECX << 5U) + 5U)
|
||||
#define X86_FEATURE_SMX ((FEAT_1_ECX << 5U) + 6U)
|
||||
#define X86_FEATURE_EST ((FEAT_1_ECX << 5U) + 7U)
|
||||
#define X86_FEATURE_TM2 ((FEAT_1_ECX << 5U) + 8U)
|
||||
#define X86_FEATURE_SSSE3 ((FEAT_1_ECX << 5U) + 9U)
|
||||
#define X86_FEATURE_CID ((FEAT_1_ECX << 5U) + 10U)
|
||||
#define X86_FEATURE_FMA ((FEAT_1_ECX << 5U) + 12U)
|
||||
#define X86_FEATURE_CX16 ((FEAT_1_ECX << 5U) + 13U)
|
||||
#define X86_FEATURE_ETPRD ((FEAT_1_ECX << 5U) + 14U)
|
||||
#define X86_FEATURE_PDCM ((FEAT_1_ECX << 5U) + 15U)
|
||||
#define X86_FEATURE_PCID ((FEAT_1_ECX << 5U) + 17U)
|
||||
#define X86_FEATURE_DCA ((FEAT_1_ECX << 5U) + 18U)
|
||||
#define X86_FEATURE_SSE4_1 ((FEAT_1_ECX << 5U) + 19U)
|
||||
#define X86_FEATURE_SSE4_2 ((FEAT_1_ECX << 5U) + 20U)
|
||||
#define X86_FEATURE_x2APIC ((FEAT_1_ECX << 5U) + 21U)
|
||||
#define X86_FEATURE_MOVBE ((FEAT_1_ECX << 5U) + 22U)
|
||||
#define X86_FEATURE_POPCNT ((FEAT_1_ECX << 5U) + 23U)
|
||||
#define X86_FEATURE_TSC_DEADLINE ((FEAT_1_ECX << 5U) + 24U)
|
||||
#define X86_FEATURE_AES ((FEAT_1_ECX << 5U) + 25U)
|
||||
#define X86_FEATURE_XSAVE ((FEAT_1_ECX << 5U) + 26U)
|
||||
#define X86_FEATURE_OSXSAVE ((FEAT_1_ECX << 5U) + 27U)
|
||||
#define X86_FEATURE_AVX ((FEAT_1_ECX << 5U) + 28U)
|
||||
|
||||
/* Intel-defined CPU features, CPUID level 0x00000001 (EDX)*/
|
||||
#define X86_FEATURE_FPU ((FEAT_1_EDX << 5) + 0)
|
||||
#define X86_FEATURE_VME ((FEAT_1_EDX << 5) + 1)
|
||||
#define X86_FEATURE_DE ((FEAT_1_EDX << 5) + 2)
|
||||
#define X86_FEATURE_PSE ((FEAT_1_EDX << 5) + 3)
|
||||
#define X86_FEATURE_TSC ((FEAT_1_EDX << 5) + 4)
|
||||
#define X86_FEATURE_MSR ((FEAT_1_EDX << 5) + 5)
|
||||
#define X86_FEATURE_PAE ((FEAT_1_EDX << 5) + 6)
|
||||
#define X86_FEATURE_MCE ((FEAT_1_EDX << 5) + 7)
|
||||
#define X86_FEATURE_CX8 ((FEAT_1_EDX << 5) + 8)
|
||||
#define X86_FEATURE_APIC ((FEAT_1_EDX << 5) + 9)
|
||||
#define X86_FEATURE_SEP ((FEAT_1_EDX << 5) + 11)
|
||||
#define X86_FEATURE_MTRR ((FEAT_1_EDX << 5) + 12)
|
||||
#define X86_FEATURE_PGE ((FEAT_1_EDX << 5) + 13)
|
||||
#define X86_FEATURE_MCA ((FEAT_1_EDX << 5) + 14)
|
||||
#define X86_FEATURE_CMOV ((FEAT_1_EDX << 5) + 15)
|
||||
#define X86_FEATURE_PAT ((FEAT_1_EDX << 5) + 16)
|
||||
#define X86_FEATURE_PSE36 ((FEAT_1_EDX << 5) + 17)
|
||||
#define X86_FEATURE_PSN ((FEAT_1_EDX << 5) + 18)
|
||||
#define X86_FEATURE_CLF ((FEAT_1_EDX << 5) + 19)
|
||||
#define X86_FEATURE_DTES ((FEAT_1_EDX << 5) + 21)
|
||||
#define X86_FEATURE_ACPI ((FEAT_1_EDX << 5) + 22)
|
||||
#define X86_FEATURE_MMX ((FEAT_1_EDX << 5) + 23)
|
||||
#define X86_FEATURE_FXSR ((FEAT_1_EDX << 5) + 24)
|
||||
#define X86_FEATURE_SSE ((FEAT_1_EDX << 5) + 25)
|
||||
#define X86_FEATURE_SSE2 ((FEAT_1_EDX << 5) + 26)
|
||||
#define X86_FEATURE_SS ((FEAT_1_EDX << 5) + 27)
|
||||
#define X86_FEATURE_HTT ((FEAT_1_EDX << 5) + 28)
|
||||
#define X86_FEATURE_TM1 ((FEAT_1_EDX << 5) + 29)
|
||||
#define X86_FEATURE_IA64 ((FEAT_1_EDX << 5) + 30)
|
||||
#define X86_FEATURE_PBE ((FEAT_1_EDX << 5) + 31)
|
||||
#define X86_FEATURE_FPU ((FEAT_1_EDX << 5U) + 0U)
|
||||
#define X86_FEATURE_VME ((FEAT_1_EDX << 5U) + 1U)
|
||||
#define X86_FEATURE_DE ((FEAT_1_EDX << 5U) + 2U)
|
||||
#define X86_FEATURE_PSE ((FEAT_1_EDX << 5U) + 3U)
|
||||
#define X86_FEATURE_TSC ((FEAT_1_EDX << 5U) + 4U)
|
||||
#define X86_FEATURE_MSR ((FEAT_1_EDX << 5U) + 5U)
|
||||
#define X86_FEATURE_PAE ((FEAT_1_EDX << 5U) + 6U)
|
||||
#define X86_FEATURE_MCE ((FEAT_1_EDX << 5U) + 7U)
|
||||
#define X86_FEATURE_CX8 ((FEAT_1_EDX << 5U) + 8U)
|
||||
#define X86_FEATURE_APIC ((FEAT_1_EDX << 5U) + 9U)
|
||||
#define X86_FEATURE_SEP ((FEAT_1_EDX << 5U) + 11U)
|
||||
#define X86_FEATURE_MTRR ((FEAT_1_EDX << 5U) + 12U)
|
||||
#define X86_FEATURE_PGE ((FEAT_1_EDX << 5U) + 13U)
|
||||
#define X86_FEATURE_MCA ((FEAT_1_EDX << 5U) + 14U)
|
||||
#define X86_FEATURE_CMOV ((FEAT_1_EDX << 5U) + 15U)
|
||||
#define X86_FEATURE_PAT ((FEAT_1_EDX << 5U) + 16U)
|
||||
#define X86_FEATURE_PSE36 ((FEAT_1_EDX << 5U) + 17U)
|
||||
#define X86_FEATURE_PSN ((FEAT_1_EDX << 5U) + 18U)
|
||||
#define X86_FEATURE_CLF ((FEAT_1_EDX << 5U) + 19U)
|
||||
#define X86_FEATURE_DTES ((FEAT_1_EDX << 5U) + 21U)
|
||||
#define X86_FEATURE_ACPI ((FEAT_1_EDX << 5U) + 22U)
|
||||
#define X86_FEATURE_MMX ((FEAT_1_EDX << 5U) + 23U)
|
||||
#define X86_FEATURE_FXSR ((FEAT_1_EDX << 5U) + 24U)
|
||||
#define X86_FEATURE_SSE ((FEAT_1_EDX << 5U) + 25U)
|
||||
#define X86_FEATURE_SSE2 ((FEAT_1_EDX << 5U) + 26U)
|
||||
#define X86_FEATURE_SS ((FEAT_1_EDX << 5U) + 27U)
|
||||
#define X86_FEATURE_HTT ((FEAT_1_EDX << 5U) + 28U)
|
||||
#define X86_FEATURE_TM1 ((FEAT_1_EDX << 5U) + 29U)
|
||||
#define X86_FEATURE_IA64 ((FEAT_1_EDX << 5U) + 30U)
|
||||
#define X86_FEATURE_PBE ((FEAT_1_EDX << 5U) + 31U)
|
||||
|
||||
/* Intel-defined CPU features, CPUID level 0x00000007 (EBX)*/
|
||||
#define X86_FEATURE_TSC_ADJ ((FEAT_7_0_EBX << 5) + 1)
|
||||
#define X86_FEATURE_SMEP ((FEAT_7_0_EBX << 5) + 7)
|
||||
#define X86_FEATURE_INVPCID ((FEAT_7_0_EBX << 5) + 10)
|
||||
#define X86_FEATURE_SMAP ((FEAT_7_0_EBX << 5) + 20)
|
||||
#define X86_FEATURE_TSC_ADJ ((FEAT_7_0_EBX << 5U) + 1U)
|
||||
#define X86_FEATURE_SMEP ((FEAT_7_0_EBX << 5U) + 7U)
|
||||
#define X86_FEATURE_INVPCID ((FEAT_7_0_EBX << 5U) + 10U)
|
||||
#define X86_FEATURE_SMAP ((FEAT_7_0_EBX << 5U) + 20U)
|
||||
|
||||
/* Intel-defined CPU features, CPUID level 0x00000007 (EDX)*/
|
||||
#define X86_FEATURE_IBRS_IBPB ((FEAT_7_0_EDX << 5) + 26)
|
||||
#define X86_FEATURE_STIBP ((FEAT_7_0_EDX << 5) + 27)
|
||||
#define X86_FEATURE_IBRS_IBPB ((FEAT_7_0_EDX << 5U) + 26U)
|
||||
#define X86_FEATURE_STIBP ((FEAT_7_0_EDX << 5U) + 27U)
|
||||
|
||||
/* Intel-defined CPU features, CPUID level 0x80000001 (EDX)*/
|
||||
#define X86_FEATURE_NX ((FEAT_8000_0001_EDX << 5) + 20)
|
||||
#define X86_FEATURE_PAGE1GB ((FEAT_8000_0001_EDX << 5) + 26)
|
||||
#define X86_FEATURE_LM ((FEAT_8000_0001_EDX << 5) + 29)
|
||||
#define X86_FEATURE_NX ((FEAT_8000_0001_EDX << 5U) + 20U)
|
||||
#define X86_FEATURE_PAGE1GB ((FEAT_8000_0001_EDX << 5U) + 26U)
|
||||
#define X86_FEATURE_LM ((FEAT_8000_0001_EDX << 5U) + 29U)
|
||||
|
||||
#endif /*__X86_CPUFEATURES_H__*/
|
||||
|
||||
@ -89,12 +89,12 @@
|
||||
#define CPUID_TLB 2
|
||||
#define CPUID_SERIALNUM 3
|
||||
#define CPUID_EXTEND_FEATURE 7
|
||||
#define CPUID_MAX_EXTENDED_FUNCTION 0x80000000
|
||||
#define CPUID_EXTEND_FUNCTION_1 0x80000001
|
||||
#define CPUID_EXTEND_FUNCTION_2 0x80000002
|
||||
#define CPUID_EXTEND_FUNCTION_3 0x80000003
|
||||
#define CPUID_EXTEND_FUNCTION_4 0x80000004
|
||||
#define CPUID_EXTEND_ADDRESS_SIZE 0x80000008
|
||||
#define CPUID_MAX_EXTENDED_FUNCTION 0x80000000U
|
||||
#define CPUID_EXTEND_FUNCTION_1 0x80000001U
|
||||
#define CPUID_EXTEND_FUNCTION_2 0x80000002U
|
||||
#define CPUID_EXTEND_FUNCTION_3 0x80000003U
|
||||
#define CPUID_EXTEND_FUNCTION_4 0x80000004U
|
||||
#define CPUID_EXTEND_ADDRESS_SIZE 0x80000008U
|
||||
|
||||
|
||||
static inline void __cpuid(uint32_t *eax, uint32_t *ebx,
|
||||
@ -112,7 +112,7 @@ static inline void cpuid(uint32_t leaf,
|
||||
uint32_t *ecx, uint32_t *edx)
|
||||
{
|
||||
*eax = leaf;
|
||||
*ecx = 0;
|
||||
*ecx = 0U;
|
||||
|
||||
__cpuid(eax, ebx, ecx, edx);
|
||||
}
|
||||
|
||||
@ -48,29 +48,29 @@
|
||||
#define CPU_CONTEXT_OFFSET_R15 104U
|
||||
#define CPU_CONTEXT_OFFSET_RDI 112U
|
||||
#define CPU_CONTEXT_OFFSET_CR0 120U
|
||||
#define CPU_CONTEXT_OFFSET_RIP 152
|
||||
#define CPU_CONTEXT_OFFSET_TSC_OFFSET 184
|
||||
#define CPU_CONTEXT_OFFSET_IA32_STAR 200
|
||||
#define CPU_CONTEXT_OFFSET_IA32_LSTAR 208
|
||||
#define CPU_CONTEXT_OFFSET_IA32_FMASK 216
|
||||
#define CPU_CONTEXT_OFFSET_IA32_KERNEL_GS_BASE 224
|
||||
#define CPU_CONTEXT_OFFSET_CS 280
|
||||
#define CPU_CONTEXT_OFFSET_DS 344
|
||||
#define CPU_CONTEXT_OFFSET_ES 376
|
||||
#define CPU_CONTEXT_OFFSET_FS 408
|
||||
#define CPU_CONTEXT_OFFSET_GS 440
|
||||
#define CPU_CONTEXT_OFFSET_TR 472
|
||||
#define CPU_CONTEXT_OFFSET_GDTR 568
|
||||
#define CPU_CONTEXT_OFFSET_FXSTORE_GUEST_AREA 608
|
||||
#define CPU_CONTEXT_OFFSET_CR2 128U
|
||||
#define CPU_CONTEXT_OFFSET_CR3 136U
|
||||
#define CPU_CONTEXT_OFFSET_CR4 144U
|
||||
#define CPU_CONTEXT_OFFSET_RIP 152U
|
||||
#define CPU_CONTEXT_OFFSET_RSP 160U
|
||||
#define CPU_CONTEXT_OFFSET_RFLAGS 168U
|
||||
#define CPU_CONTEXT_OFFSET_TSC_OFFSET 184U
|
||||
#define CPU_CONTEXT_OFFSET_IA32_SPEC_CTRL 192U
|
||||
#define CPU_CONTEXT_OFFSET_IA32_STAR 200U
|
||||
#define CPU_CONTEXT_OFFSET_IA32_LSTAR 208U
|
||||
#define CPU_CONTEXT_OFFSET_IA32_FMASK 216U
|
||||
#define CPU_CONTEXT_OFFSET_IA32_KERNEL_GS_BASE 224U
|
||||
#define CPU_CONTEXT_OFFSET_CS 280U
|
||||
#define CPU_CONTEXT_OFFSET_SS 312U
|
||||
#define CPU_CONTEXT_OFFSET_DS 344U
|
||||
#define CPU_CONTEXT_OFFSET_ES 376U
|
||||
#define CPU_CONTEXT_OFFSET_FS 408U
|
||||
#define CPU_CONTEXT_OFFSET_GS 440U
|
||||
#define CPU_CONTEXT_OFFSET_TR 472U
|
||||
#define CPU_CONTEXT_OFFSET_IDTR 504U
|
||||
#define CPU_CONTEXT_OFFSET_LDTR 536U
|
||||
#define CPU_CONTEXT_OFFSET_GDTR 568U
|
||||
#define CPU_CONTEXT_OFFSET_FXSTORE_GUEST_AREA 608U
|
||||
|
||||
/*sizes of various registers within the VCPU data structure */
|
||||
#define VMX_CPU_S_FXSAVE_GUEST_AREA_SIZE GUEST_STATE_AREA_SIZE
|
||||
|
||||
Loading…
Reference in New Issue
Block a user