HV:CPU: Add 'U/UL' for unsigned const value

According to MISRA C:2012, suffix 'U/UL' shall be for unsigned const value, the member of enum variable should not be used to compare with integer variable. Add 'U/UL' for unsigned const value in the CPU module; Use Macro insteading of enum feature_word since the member of feature_word is used to compare with integer variable; Use hex number insteading of Macro in the assembly code. V1-->V2: Update the suffix of some constant value as 'UL' according to its'storage variable; Split MACRO updates used in the assembly code in other patch. Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2025-09-23 17:58:30 +00:00 · 2018-07-06 13:49:41 +08:00
parent 21f0bddff8
commit 474e9af216
8 changed files with 191 additions and 194 deletions
--- a/hypervisor/arch/x86/cpu.c
+++ b/hypervisor/arch/x86/cpu.c
@@ -28,7 +28,7 @@ uint64_t pcpu_sync = 0UL;
 volatile uint16_t up_count = 0U;

 /* physical cpu active bitmap, support up to 64 cpus */
-uint64_t pcpu_active_bitmap = 0;
+uint64_t pcpu_active_bitmap = 0UL;

 uint64_t trampoline_start16_paddr;

@@ -77,7 +77,7 @@ inline bool cpu_has_cap(uint32_t bit)
 	if (feat_idx >= FEATURE_WORDS)
 		return false;

-	return ((boot_cpu_data.cpuid_leaves[feat_idx] & (1 << feat_bit)) != 0U);
+	return ((boot_cpu_data.cpuid_leaves[feat_idx] & (1U << feat_bit)) != 0U);
 }

 static inline bool get_monitor_cap(void)
@@ -111,15 +111,15 @@ static void get_cpu_capabilities(void)
 	cpuid(CPUID_FEATURES, &eax, &unused,
 		&boot_cpu_data.cpuid_leaves[FEAT_1_ECX],
 		&boot_cpu_data.cpuid_leaves[FEAT_1_EDX]);
-	family = (eax >> 8) & 0xffU;
+	family = (eax >> 8U) & 0xffU;
 	if (family == 0xFU)
-		family += (eax >> 20) & 0xffU;
+		family += (eax >> 20U) & 0xffU;
 	boot_cpu_data.x86 = family;

-	model = (eax >> 4) & 0xfU;
+	model = (eax >> 4U) & 0xfU;
 	if (family >= 0x06U)
-		model += ((eax >> 16) & 0xfU) << 4;
-	boot_cpu_data.x86_model = model;
+		model += ((eax >> 16U) & 0xfU) << 4U;
+	boot_cpu_data.x86_model = (uint8_t)model;


 	cpuid(CPUID_EXTEND_FEATURE, &unused,
@@ -144,8 +144,8 @@ static void get_cpu_capabilities(void)
 			/* EAX bits 07-00: #Physical Address Bits
 			 *     bits 15-08: #Linear Address Bits
 			 */
-			boot_cpu_data.x86_virt_bits = (eax >> 8) & 0xffU;
-			boot_cpu_data.x86_phys_bits = eax & 0xffU;
+			boot_cpu_data.x86_virt_bits = (uint8_t)((eax >> 8U) & 0xffU);
+			boot_cpu_data.x86_phys_bits = (uint8_t)(eax & 0xffU);
 			boot_cpu_data.physical_address_mask =
 				get_address_mask(boot_cpu_data.x86_phys_bits);
 	}
@@ -317,7 +317,7 @@ static void cpu_set_current_state(uint16_t pcpu_id, enum cpu_state state)
 #ifdef STACK_PROTECTOR
 static uint64_t get_random_value(void)
 {
-	uint64_t random = 0;
+	uint64_t random = 0UL;

 	asm volatile ("1: rdrand %%rax\n"
 			"jnc 1b\n"
@@ -374,7 +374,7 @@ void bsp_boot_init(void)
 	*  is matching the actual offset!
 	*/
 	ASSERT(sizeof(struct trusty_startup_param)
-			+ sizeof(struct key_info) < 0x1000,
+			+ sizeof(struct key_info) < 0x1000U,
 		"trusty_startup_param + key_info > 1Page size(4KB)!");

 	ASSERT(NR_WORLD == 2, "Only 2 Worlds supported!");
@@ -507,7 +507,7 @@ static void bsp_boot_post(void)

 	pr_acrnlog("Detect processor: %s", boot_cpu_data.model_name);

-	pr_dbg("Core %d is up", CPU_BOOT_ID);
+	pr_dbg("Core %hu is up", CPU_BOOT_ID);

 	if (hardware_detect_support() != 0) {
 		pr_fatal("hardware not support!\n");
@@ -606,7 +606,7 @@ static void cpu_secondary_post(void)
 	/* Make sure rdtsc is enabled */
 	check_tsc();

-	pr_dbg("Core %d is up", get_cpu_id());
+	pr_dbg("Core %hu is up", get_cpu_id());

 	cpu_xsave_init();

@@ -616,7 +616,7 @@ static void cpu_secondary_post(void)
 	timer_init();

 	/* Wait for boot processor to signal all secondary cores to continue */
-	pcpu_sync_sleep(&pcpu_sync, 0);
+	pcpu_sync_sleep(&pcpu_sync, 0UL);

 	ret = hv_main(get_cpu_id());
 	if (ret != 0)
@@ -728,10 +728,10 @@ void start_cpus()
 	timeout = CONFIG_CPU_UP_TIMEOUT * 1000;
 	while ((up_count != expected_up) && (timeout != 0U)) {
 		/* Delay 10us */
-		udelay(10);
+		udelay(10U);

 		/* Decrement timeout value */
-		timeout -= 10;
+		timeout -= 10U;
 	}

 	/* Check to see if all expected CPUs are actually up */
@@ -761,10 +761,10 @@ void stop_cpus()
 	expected_up = 1U;
 	while ((up_count != expected_up) && (timeout != 0U)) {
 		/* Delay 10us */
-		udelay(10);
+		udelay(10U);

 		/* Decrement timeout value */
-		timeout -= 10;
+		timeout -= 10U;
 	}

 	if (up_count != expected_up) {
@@ -864,7 +864,7 @@ static bool is_ctrl_setting_allowed(uint64_t msr_val, uint32_t ctrl)
 	 * - bitX in ctrl can be set 1
 	 *   only if bit 32+X in msr_val is 1
 	 */
-	return ((((uint32_t)(msr_val >> 32)) & ctrl) == ctrl);
+	return ((((uint32_t)(msr_val >> 32UL)) & ctrl) == ctrl);
 }

 static void vapic_cap_detect(void)
@@ -908,17 +908,17 @@ static void vapic_cap_detect(void)

 bool is_vapic_supported(void)
 {
-	return ((cpu_caps.vapic_features & VAPIC_FEATURE_VIRT_ACCESS) != 0);
+	return ((cpu_caps.vapic_features & VAPIC_FEATURE_VIRT_ACCESS) != 0U);
 }

 bool is_vapic_intr_delivery_supported(void)
 {
-	return ((cpu_caps.vapic_features & VAPIC_FEATURE_INTR_DELIVERY) != 0);
+	return ((cpu_caps.vapic_features & VAPIC_FEATURE_INTR_DELIVERY) != 0U);
 }

 bool is_vapic_virt_reg_supported(void)
 {
-	return ((cpu_caps.vapic_features & VAPIC_FEATURE_VIRT_REG) != 0);
+	return ((cpu_caps.vapic_features & VAPIC_FEATURE_VIRT_REG) != 0U);
 }

 static void cpu_xsave_init(void)
--- a/hypervisor/arch/x86/cpu_state_tbl.c
+++ b/hypervisor/arch/x86/cpu_state_tbl.c
@@ -8,67 +8,67 @@

 /* The table includes cpu px info of Intel A3960 SoC */
 static const struct cpu_px_data px_a3960[] = {
-	{0x960, 0, 0xA, 0xA, 0x1800, 0x1800}, /* P0 */
-	{0x8FC, 0, 0xA, 0xA, 0x1700, 0x1700}, /* P1 */
-	{0x898, 0, 0xA, 0xA, 0x1600, 0x1600}, /* P2 */
-	{0x834, 0, 0xA, 0xA, 0x1500, 0x1500}, /* P3 */
-	{0x7D0, 0, 0xA, 0xA, 0x1400, 0x1400}, /* P4 */
-	{0x76C, 0, 0xA, 0xA, 0x1300, 0x1300}, /* P5 */
-	{0x708, 0, 0xA, 0xA, 0x1200, 0x1200}, /* P6 */
-	{0x6A4, 0, 0xA, 0xA, 0x1100, 0x1100}, /* P7 */
-	{0x640, 0, 0xA, 0xA, 0x1000, 0x1000}, /* P8 */
-	{0x5DC, 0, 0xA, 0xA, 0x0F00, 0x0F00}, /* P9 */
-	{0x578, 0, 0xA, 0xA, 0x0E00, 0x0E00}, /* P10 */
-	{0x514, 0, 0xA, 0xA, 0x0D00, 0x0D00}, /* P11 */
-	{0x4B0, 0, 0xA, 0xA, 0x0C00, 0x0C00}, /* P12 */
-	{0x44C, 0, 0xA, 0xA, 0x0B00, 0x0B00}, /* P13 */
-	{0x3E8, 0, 0xA, 0xA, 0x0A00, 0x0A00}, /* P14 */
-	{0x384, 0, 0xA, 0xA, 0x0900, 0x0900}, /* P15 */
-	{0x320, 0, 0xA, 0xA, 0x0800, 0x0800}  /* P16 */
+	{0x960UL, 0UL, 0xAUL, 0xAUL, 0x1800UL, 0x1800UL}, /* P0 */
+	{0x8FCUL, 0UL, 0xAUL, 0xAUL, 0x1700UL, 0x1700UL}, /* P1 */
+	{0x898UL, 0UL, 0xAUL, 0xAUL, 0x1600UL, 0x1600UL}, /* P2 */
+	{0x834UL, 0UL, 0xAUL, 0xAUL, 0x1500UL, 0x1500UL}, /* P3 */
+	{0x7D0UL, 0UL, 0xAUL, 0xAUL, 0x1400UL, 0x1400UL}, /* P4 */
+	{0x76CUL, 0UL, 0xAUL, 0xAUL, 0x1300UL, 0x1300UL}, /* P5 */
+	{0x708UL, 0UL, 0xAUL, 0xAUL, 0x1200UL, 0x1200UL}, /* P6 */
+	{0x6A4UL, 0UL, 0xAUL, 0xAUL, 0x1100UL, 0x1100UL}, /* P7 */
+	{0x640UL, 0UL, 0xAUL, 0xAUL, 0x1000UL, 0x1000UL}, /* P8 */
+	{0x5DCUL, 0UL, 0xAUL, 0xAUL, 0x0F00UL, 0x0F00UL}, /* P9 */
+	{0x578UL, 0UL, 0xAUL, 0xAUL, 0x0E00UL, 0x0E00UL}, /* P10 */
+	{0x514UL, 0UL, 0xAUL, 0xAUL, 0x0D00UL, 0x0D00UL}, /* P11 */
+	{0x4B0UL, 0UL, 0xAUL, 0xAUL, 0x0C00UL, 0x0C00UL}, /* P12 */
+	{0x44CUL, 0UL, 0xAUL, 0xAUL, 0x0B00UL, 0x0B00UL}, /* P13 */
+	{0x3E8UL, 0UL, 0xAUL, 0xAUL, 0x0A00UL, 0x0A00UL}, /* P14 */
+	{0x384UL, 0UL, 0xAUL, 0xAUL, 0x0900UL, 0x0900UL}, /* P15 */
+	{0x320UL, 0UL, 0xAUL, 0xAUL, 0x0800UL, 0x0800UL}  /* P16 */
 };

 /* The table includes cpu cx info of Intel A3960 SoC */
 static const struct cpu_cx_data cx_a3960[] = {
-	{{SPACE_FFixedHW,  0x0, 0, 0,     0}, 0x1, 0x1, 0x3E8}, /* C1 */
-	{{SPACE_SYSTEM_IO, 0x8, 0, 0, 0x415}, 0x2, 0x32, 0x0A}, /* C2 */
-	{{SPACE_SYSTEM_IO, 0x8, 0, 0, 0x419}, 0x3, 0x96, 0x0A}  /* C3 */
+	{{SPACE_FFixedHW,  0x0U, 0U, 0U,     0UL}, 0x1U, 0x1U, 0x3E8UL}, /* C1 */
+	{{SPACE_SYSTEM_IO, 0x8U, 0U, 0U, 0x415UL}, 0x2U, 0x32U, 0x0AUL}, /* C2 */
+	{{SPACE_SYSTEM_IO, 0x8U, 0U, 0U, 0x419UL}, 0x3U, 0x96U, 0x0AUL}  /* C3 */
 };

 /* The table includes cpu px info of Intel A3950 SoC */
 static const struct cpu_px_data px_a3950[] = {
-	{0x7D0, 0, 0xA, 0xA, 0x1400, 0x1400}, /* P0 */
-	{0x76C, 0, 0xA, 0xA, 0x1300, 0x1300}, /* P1 */
-	{0x708, 0, 0xA, 0xA, 0x1200, 0x1200}, /* P2 */
-	{0x6A4, 0, 0xA, 0xA, 0x1100, 0x1100}, /* P3 */
-	{0x640, 0, 0xA, 0xA, 0x1000, 0x1000}, /* P4 */
-	{0x5DC, 0, 0xA, 0xA, 0x0F00, 0x0F00}, /* P5 */
-	{0x578, 0, 0xA, 0xA, 0x0E00, 0x0E00}, /* P6 */
-	{0x514, 0, 0xA, 0xA, 0x0D00, 0x0D00}, /* P7 */
-	{0x4B0, 0, 0xA, 0xA, 0x0C00, 0x0C00}, /* P8 */
-	{0x44C, 0, 0xA, 0xA, 0x0B00, 0x0B00}, /* P9 */
-	{0x3E8, 0, 0xA, 0xA, 0x0A00, 0x0A00}, /* P10 */
-	{0x384, 0, 0xA, 0xA, 0x0900, 0x0900}, /* P11 */
-	{0x320, 0, 0xA, 0xA, 0x0800, 0x0800}  /* P12 */
+	{0x7D0UL, 0UL, 0xAUL, 0xAUL, 0x1400UL, 0x1400UL}, /* P0 */
+	{0x76CUL, 0UL, 0xAUL, 0xAUL, 0x1300UL, 0x1300UL}, /* P1 */
+	{0x708UL, 0UL, 0xAUL, 0xAUL, 0x1200UL, 0x1200UL}, /* P2 */
+	{0x6A4UL, 0UL, 0xAUL, 0xAUL, 0x1100UL, 0x1100UL}, /* P3 */
+	{0x640UL, 0UL, 0xAUL, 0xAUL, 0x1000UL, 0x1000UL}, /* P4 */
+	{0x5DCUL, 0UL, 0xAUL, 0xAUL, 0x0F00UL, 0x0F00UL}, /* P5 */
+	{0x578UL, 0UL, 0xAUL, 0xAUL, 0x0E00UL, 0x0E00UL}, /* P6 */
+	{0x514UL, 0UL, 0xAUL, 0xAUL, 0x0D00UL, 0x0D00UL}, /* P7 */
+	{0x4B0UL, 0UL, 0xAUL, 0xAUL, 0x0C00UL, 0x0C00UL}, /* P8 */
+	{0x44CUL, 0UL, 0xAUL, 0xAUL, 0x0B00UL, 0x0B00UL}, /* P9 */
+	{0x3E8UL, 0UL, 0xAUL, 0xAUL, 0x0A00UL, 0x0A00UL}, /* P10 */
+	{0x384UL, 0UL, 0xAUL, 0xAUL, 0x0900UL, 0x0900UL}, /* P11 */
+	{0x320UL, 0UL, 0xAUL, 0xAUL, 0x0800UL, 0x0800UL}  /* P12 */
 };

 /* The table includes cpu px info of Intel J3455 SoC */
 static const struct cpu_px_data px_j3455[] = {
-	{0x5DD, 0, 0xA, 0xA, 0x1700, 0x1700}, /* P0 */
-	{0x5DC, 0, 0xA, 0xA, 0x0F00, 0x0F00}, /* P1 */
-	{0x578, 0, 0xA, 0xA, 0x0E00, 0x0E00}, /* P2 */
-	{0x514, 0, 0xA, 0xA, 0x0D00, 0x0D00}, /* P3 */
-	{0x4B0, 0, 0xA, 0xA, 0x0C00, 0x0C00}, /* P4 */
-	{0x44C, 0, 0xA, 0xA, 0x0B00, 0x0B00}, /* P5 */
-	{0x3E8, 0, 0xA, 0xA, 0x0A00, 0x0A00}, /* P6 */
-	{0x384, 0, 0xA, 0xA, 0x0900, 0x0900}, /* P7 */
-	{0x320, 0, 0xA, 0xA, 0x0800, 0x0800}  /* P8 */
+	{0x5DDUL, 0UL, 0xAUL, 0xAUL, 0x1700UL, 0x1700UL}, /* P0 */
+	{0x5DCUL, 0UL, 0xAUL, 0xAUL, 0x0F00UL, 0x0F00UL}, /* P1 */
+	{0x578UL, 0UL, 0xAUL, 0xAUL, 0x0E00UL, 0x0E00UL}, /* P2 */
+	{0x514UL, 0UL, 0xAUL, 0xAUL, 0x0D00UL, 0x0D00UL}, /* P3 */
+	{0x4B0UL, 0UL, 0xAUL, 0xAUL, 0x0C00UL, 0x0C00UL}, /* P4 */
+	{0x44CUL, 0UL, 0xAUL, 0xAUL, 0x0B00UL, 0x0B00UL}, /* P5 */
+	{0x3E8UL, 0UL, 0xAUL, 0xAUL, 0x0A00UL, 0x0A00UL}, /* P6 */
+	{0x384UL, 0UL, 0xAUL, 0xAUL, 0x0900UL, 0x0900UL}, /* P7 */
+	{0x320UL, 0UL, 0xAUL, 0xAUL, 0x0800UL, 0x0800UL}  /* P8 */
 };

 /* The table includes cpu cx info of Intel J3455 SoC */
 static const struct cpu_cx_data cx_j3455[] = {
-	{{SPACE_FFixedHW, 0x1, 0x2, 0x1, 0x01}, 0x1, 0x1, 0x3E8}, /* C1 */
-	{{SPACE_FFixedHW, 0x1, 0x2, 0x1, 0x21}, 0x2, 0x32, 0x0A}, /* C2 */
-	{{SPACE_FFixedHW, 0x1, 0x2, 0x1, 0x60}, 0x3, 0x96, 0x0A}  /* C3 */
+	{{SPACE_FFixedHW, 0x1U, 0x2U, 0x1U, 0x01UL}, 0x1U, 0x1U, 0x3E8UL}, /* C1 */
+	{{SPACE_FFixedHW, 0x1U, 0x2U, 0x1U, 0x21UL}, 0x2U, 0x32U, 0x0AUL}, /* C2 */
+	{{SPACE_FFixedHW, 0x1U, 0x2U, 0x1U, 0x60UL}, 0x3U, 0x96U, 0x0AUL}  /* C3 */
 };

 static const struct cpu_state_table {
@@ -113,7 +113,7 @@ void load_cpu_state_data(void)
 	int tbl_idx;
 	const struct cpu_state_info *state_info;

-	(void)memset(&boot_cpu_data.state_info, 0,
+	(void)memset(&boot_cpu_data.state_info, 0U,
 			sizeof(struct cpu_state_info));

 	tbl_idx = get_state_tbl_idx(boot_cpu_data.model_name);
--- a/hypervisor/arch/x86/cpuid.c
+++ b/hypervisor/arch/x86/cpuid.c
@@ -36,7 +36,7 @@ static inline struct vcpuid_entry *find_vcpuid_entry(struct vcpu *vcpu,
 	if (entry == NULL) {
 		uint32_t limit;

-		if ((leaf & 0x80000000) != 0U)
+		if ((leaf & 0x80000000U) != 0U)
 			limit = vm->vcpuid_xlevel;
 		else
 			limit = vm->vcpuid_level;
@@ -160,7 +160,7 @@ int set_vcpuid_entries(struct vm *vm)
 	uint32_t limit;
 	uint32_t i, j;

-	init_vcpuid_entry(vm, 0, 0, 0, &entry);
+	init_vcpuid_entry(vm, 0U, 0U, 0U, &entry);
 	result = set_vcpuid_entry(vm, &entry);
 	if (result != 0)
 		return result;
@@ -176,7 +176,7 @@ int set_vcpuid_entries(struct vm *vm)
 		{
 			uint32_t times;

-			init_vcpuid_entry(vm, i, 0,
+			init_vcpuid_entry(vm, i, 0U,
 				CPUID_CHECK_SUBLEAF, &entry);
 			result = set_vcpuid_entry(vm, &entry);
 			if (result != 0)
@@ -212,7 +212,7 @@ int set_vcpuid_entries(struct vm *vm)
 			break;

 		default:
-			init_vcpuid_entry(vm, i, 0, 0, &entry);
+			init_vcpuid_entry(vm, i, 0U, 0U, &entry);
 			result = set_vcpuid_entry(vm, &entry);
 			if (result != 0)
 				return result;
@@ -220,24 +220,24 @@ int set_vcpuid_entries(struct vm *vm)
 		}
 	}

-	init_vcpuid_entry(vm, 0x40000000, 0, 0, &entry);
+	init_vcpuid_entry(vm, 0x40000000U, 0U, 0U, &entry);
 	result = set_vcpuid_entry(vm, &entry);
 	if (result != 0)
 		return result;

-	init_vcpuid_entry(vm, 0x40000010, 0, 0, &entry);
+	init_vcpuid_entry(vm, 0x40000010U, 0U, 0U, &entry);
 	result = set_vcpuid_entry(vm, &entry);
 	if (result != 0)
 		return result;

-	init_vcpuid_entry(vm, 0x80000000, 0, 0, &entry);
+	init_vcpuid_entry(vm, 0x80000000U, 0U, 0U, &entry);
 	result = set_vcpuid_entry(vm, &entry);
 	if (result != 0)
 		return result;

 	vm->vcpuid_xlevel = limit = entry.eax;
 	for (i = 0x80000001U; i <= limit; i++) {
-		init_vcpuid_entry(vm, i, 0, 0, &entry);
+		init_vcpuid_entry(vm, i, 0U, 0U, &entry);
 		result = set_vcpuid_entry(vm, &entry);
 		if (result != 0)
 			return result;
@@ -309,7 +309,7 @@ void guest_cpuid(struct vcpu *vcpu,
 			uint64_t cr4;
 			/*read guest CR4*/
 			cr4 = exec_vmread(VMX_GUEST_CR4);
-			if ((cr4 & CR4_OSXSAVE) != 0U)
+			if ((cr4 & CR4_OSXSAVE) != 0UL)
 				*ecx |= CPUID_ECX_OSXSAVE;
 		}
 		break;