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HV:CPU: Add 'U/UL' for unsigned const value
According to MISRA C:2012, suffix 'U/UL' shall be for
unsigned const value, the member of enum variable should
not be used to compare with integer variable.
Add 'U/UL' for unsigned const value in the CPU module;
Use Macro insteading of enum feature_word since the member
of feature_word is used to compare with integer variable;
Use hex number insteading of Macro in the assembly code.
V1-->V2:
Update the suffix of some constant value as 'UL'
according to its'storage variable;
Split MACRO updates used in the assembly code
in other patch.
Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Xiangyang Wu
wenlingz
@@ -67,25 +67,25 @@
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#define CR3_PCD (1U<<4) /* page-level cache disable */
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/* CR4 register definitions */
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#define CR4_VME (1U<<0) /* virtual 8086 mode extensions */
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#define CR4_PVI (1U<<1) /* protected mode virtual interrupts */
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#define CR4_TSD (1U<<2) /* time stamp disable */
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#define CR4_DE (1U<<3) /* debugging extensions */
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#define CR4_PSE (1U<<4) /* page size extensions */
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#define CR4_PAE (1U<<5) /* physical address extensions */
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#define CR4_MCE (1U<<6) /* machine check enable */
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#define CR4_PGE (1U<<7) /* page global enable */
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#define CR4_PCE (1U<<8)
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#define CR4_VME (1UL<<0) /* virtual 8086 mode extensions */
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#define CR4_PVI (1UL<<1) /* protected mode virtual interrupts */
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#define CR4_TSD (1UL<<2) /* time stamp disable */
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#define CR4_DE (1UL<<3) /* debugging extensions */
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#define CR4_PSE (1UL<<4) /* page size extensions */
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#define CR4_PAE (1UL<<5) /* physical address extensions */
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#define CR4_MCE (1UL<<6) /* machine check enable */
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#define CR4_PGE (1UL<<7) /* page global enable */
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#define CR4_PCE (1UL<<8)
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/* performance monitoring counter enable */
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#define CR4_OSFXSR (1U<<9) /* OS support for FXSAVE/FXRSTOR */
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#define CR4_OSXMMEXCPT (1U<<10)
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#define CR4_OSFXSR (1UL<<9) /* OS support for FXSAVE/FXRSTOR */
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#define CR4_OSXMMEXCPT (1UL<<10)
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/* OS support for unmasked SIMD floating point exceptions */
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#define CR4_VMXE (1U<<13) /* VMX enable */
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#define CR4_SMXE (1U<<14) /* SMX enable */
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#define CR4_PCIDE (1U<<17) /* PCID enable */
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#define CR4_OSXSAVE (1U<<18)
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#define CR4_SMEP (1U<<20)
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#define CR4_SMAP (1U<<21)
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#define CR4_VMXE (1UL<<13) /* VMX enable */
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#define CR4_SMXE (1UL<<14) /* SMX enable */
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#define CR4_PCIDE (1UL<<17) /* PCID enable */
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#define CR4_OSXSAVE (1UL<<18)
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#define CR4_SMEP (1UL<<20)
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#define CR4_SMAP (1UL<<21)
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/* XSAVE and Processor Extended States enable bit */
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@@ -197,18 +197,15 @@ extern spinlock_t trampoline_spinlock;
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((uint64_t)_ld_cpu_data_end - (uint64_t)(_ld_cpu_data_start))
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/* CPUID feature words */
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enum feature_word {
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FEAT_1_ECX = 0, /* CPUID[1].ECX */
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FEAT_1_EDX, /* CPUID[1].EDX */
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FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */
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FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */
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FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */
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FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */
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FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */
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FEAT_8000_0008_EBX, /* CPUID[8000_0008].EAX */
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FEATURE_WORDS,
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};
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#define FEAT_1_ECX 0U /* CPUID[1].ECX */
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#define FEAT_1_EDX 1U /* CPUID[1].EDX */
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#define FEAT_7_0_EBX 2U /* CPUID[EAX=7,ECX=0].EBX */
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#define FEAT_7_0_ECX 3U /* CPUID[EAX=7,ECX=0].ECX */
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#define FEAT_7_0_EDX 4U /* CPUID[EAX=7,ECX=0].EDX */
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#define FEAT_8000_0001_ECX 5U /* CPUID[8000_0001].ECX */
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#define FEAT_8000_0001_EDX 6U /* CPUID[8000_0001].EDX */
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#define FEAT_8000_0008_EBX 7U /* CPUID[8000_0008].EAX */
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#define FEATURE_WORDS 8U
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/**
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*The invalid cpu_id (INVALID_CPU_ID) is error
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*code for error handling, this means that
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@@ -8,79 +8,79 @@
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#define __X86_CPUFEATURES_H__
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/* Intel-defined CPU features, CPUID level 0x00000001 (ECX)*/
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#define X86_FEATURE_SSE3 ((FEAT_1_ECX << 5) + 0)
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#define X86_FEATURE_PCLMUL ((FEAT_1_ECX << 5) + 1)
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#define X86_FEATURE_DTES64 ((FEAT_1_ECX << 5) + 2)
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#define X86_FEATURE_MONITOR ((FEAT_1_ECX << 5) + 3)
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#define X86_FEATURE_DS_CPL ((FEAT_1_ECX << 5) + 4)
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#define X86_FEATURE_VMX ((FEAT_1_ECX << 5) + 5)
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#define X86_FEATURE_SMX ((FEAT_1_ECX << 5) + 6)
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#define X86_FEATURE_EST ((FEAT_1_ECX << 5) + 7)
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#define X86_FEATURE_TM2 ((FEAT_1_ECX << 5) + 8)
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#define X86_FEATURE_SSSE3 ((FEAT_1_ECX << 5) + 9)
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#define X86_FEATURE_CID ((FEAT_1_ECX << 5) + 10)
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#define X86_FEATURE_FMA ((FEAT_1_ECX << 5) + 12)
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#define X86_FEATURE_CX16 ((FEAT_1_ECX << 5) + 13)
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#define X86_FEATURE_ETPRD ((FEAT_1_ECX << 5) + 14)
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#define X86_FEATURE_PDCM ((FEAT_1_ECX << 5) + 15)
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#define X86_FEATURE_PCID ((FEAT_1_ECX << 5) + 17)
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#define X86_FEATURE_DCA ((FEAT_1_ECX << 5) + 18)
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#define X86_FEATURE_SSE4_1 ((FEAT_1_ECX << 5) + 19)
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#define X86_FEATURE_SSE4_2 ((FEAT_1_ECX << 5) + 20)
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#define X86_FEATURE_x2APIC ((FEAT_1_ECX << 5) + 21)
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#define X86_FEATURE_MOVBE ((FEAT_1_ECX << 5) + 22)
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#define X86_FEATURE_POPCNT ((FEAT_1_ECX << 5) + 23)
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#define X86_FEATURE_TSC_DEADLINE ((FEAT_1_ECX << 5) + 24)
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#define X86_FEATURE_AES ((FEAT_1_ECX << 5) + 25)
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#define X86_FEATURE_XSAVE ((FEAT_1_ECX << 5) + 26)
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#define X86_FEATURE_OSXSAVE ((FEAT_1_ECX << 5) + 27)
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#define X86_FEATURE_AVX ((FEAT_1_ECX << 5) + 28)
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#define X86_FEATURE_SSE3 ((FEAT_1_ECX << 5U) + 0U)
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#define X86_FEATURE_PCLMUL ((FEAT_1_ECX << 5U) + 1U)
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#define X86_FEATURE_DTES64 ((FEAT_1_ECX << 5U) + 2U)
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#define X86_FEATURE_MONITOR ((FEAT_1_ECX << 5U) + 3U)
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#define X86_FEATURE_DS_CPL ((FEAT_1_ECX << 5U) + 4U)
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#define X86_FEATURE_VMX ((FEAT_1_ECX << 5U) + 5U)
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#define X86_FEATURE_SMX ((FEAT_1_ECX << 5U) + 6U)
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#define X86_FEATURE_EST ((FEAT_1_ECX << 5U) + 7U)
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#define X86_FEATURE_TM2 ((FEAT_1_ECX << 5U) + 8U)
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#define X86_FEATURE_SSSE3 ((FEAT_1_ECX << 5U) + 9U)
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#define X86_FEATURE_CID ((FEAT_1_ECX << 5U) + 10U)
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#define X86_FEATURE_FMA ((FEAT_1_ECX << 5U) + 12U)
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#define X86_FEATURE_CX16 ((FEAT_1_ECX << 5U) + 13U)
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#define X86_FEATURE_ETPRD ((FEAT_1_ECX << 5U) + 14U)
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#define X86_FEATURE_PDCM ((FEAT_1_ECX << 5U) + 15U)
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#define X86_FEATURE_PCID ((FEAT_1_ECX << 5U) + 17U)
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#define X86_FEATURE_DCA ((FEAT_1_ECX << 5U) + 18U)
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#define X86_FEATURE_SSE4_1 ((FEAT_1_ECX << 5U) + 19U)
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#define X86_FEATURE_SSE4_2 ((FEAT_1_ECX << 5U) + 20U)
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#define X86_FEATURE_x2APIC ((FEAT_1_ECX << 5U) + 21U)
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#define X86_FEATURE_MOVBE ((FEAT_1_ECX << 5U) + 22U)
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#define X86_FEATURE_POPCNT ((FEAT_1_ECX << 5U) + 23U)
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#define X86_FEATURE_TSC_DEADLINE ((FEAT_1_ECX << 5U) + 24U)
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#define X86_FEATURE_AES ((FEAT_1_ECX << 5U) + 25U)
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#define X86_FEATURE_XSAVE ((FEAT_1_ECX << 5U) + 26U)
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#define X86_FEATURE_OSXSAVE ((FEAT_1_ECX << 5U) + 27U)
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#define X86_FEATURE_AVX ((FEAT_1_ECX << 5U) + 28U)
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/* Intel-defined CPU features, CPUID level 0x00000001 (EDX)*/
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#define X86_FEATURE_FPU ((FEAT_1_EDX << 5) + 0)
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#define X86_FEATURE_VME ((FEAT_1_EDX << 5) + 1)
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#define X86_FEATURE_DE ((FEAT_1_EDX << 5) + 2)
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#define X86_FEATURE_PSE ((FEAT_1_EDX << 5) + 3)
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#define X86_FEATURE_TSC ((FEAT_1_EDX << 5) + 4)
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#define X86_FEATURE_MSR ((FEAT_1_EDX << 5) + 5)
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#define X86_FEATURE_PAE ((FEAT_1_EDX << 5) + 6)
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#define X86_FEATURE_MCE ((FEAT_1_EDX << 5) + 7)
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#define X86_FEATURE_CX8 ((FEAT_1_EDX << 5) + 8)
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#define X86_FEATURE_APIC ((FEAT_1_EDX << 5) + 9)
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#define X86_FEATURE_SEP ((FEAT_1_EDX << 5) + 11)
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#define X86_FEATURE_MTRR ((FEAT_1_EDX << 5) + 12)
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#define X86_FEATURE_PGE ((FEAT_1_EDX << 5) + 13)
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#define X86_FEATURE_MCA ((FEAT_1_EDX << 5) + 14)
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#define X86_FEATURE_CMOV ((FEAT_1_EDX << 5) + 15)
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#define X86_FEATURE_PAT ((FEAT_1_EDX << 5) + 16)
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#define X86_FEATURE_PSE36 ((FEAT_1_EDX << 5) + 17)
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#define X86_FEATURE_PSN ((FEAT_1_EDX << 5) + 18)
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#define X86_FEATURE_CLF ((FEAT_1_EDX << 5) + 19)
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#define X86_FEATURE_DTES ((FEAT_1_EDX << 5) + 21)
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#define X86_FEATURE_ACPI ((FEAT_1_EDX << 5) + 22)
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#define X86_FEATURE_MMX ((FEAT_1_EDX << 5) + 23)
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#define X86_FEATURE_FXSR ((FEAT_1_EDX << 5) + 24)
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#define X86_FEATURE_SSE ((FEAT_1_EDX << 5) + 25)
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#define X86_FEATURE_SSE2 ((FEAT_1_EDX << 5) + 26)
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#define X86_FEATURE_SS ((FEAT_1_EDX << 5) + 27)
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#define X86_FEATURE_HTT ((FEAT_1_EDX << 5) + 28)
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#define X86_FEATURE_TM1 ((FEAT_1_EDX << 5) + 29)
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#define X86_FEATURE_IA64 ((FEAT_1_EDX << 5) + 30)
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#define X86_FEATURE_PBE ((FEAT_1_EDX << 5) + 31)
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#define X86_FEATURE_FPU ((FEAT_1_EDX << 5U) + 0U)
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#define X86_FEATURE_VME ((FEAT_1_EDX << 5U) + 1U)
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#define X86_FEATURE_DE ((FEAT_1_EDX << 5U) + 2U)
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#define X86_FEATURE_PSE ((FEAT_1_EDX << 5U) + 3U)
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#define X86_FEATURE_TSC ((FEAT_1_EDX << 5U) + 4U)
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#define X86_FEATURE_MSR ((FEAT_1_EDX << 5U) + 5U)
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#define X86_FEATURE_PAE ((FEAT_1_EDX << 5U) + 6U)
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#define X86_FEATURE_MCE ((FEAT_1_EDX << 5U) + 7U)
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#define X86_FEATURE_CX8 ((FEAT_1_EDX << 5U) + 8U)
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#define X86_FEATURE_APIC ((FEAT_1_EDX << 5U) + 9U)
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#define X86_FEATURE_SEP ((FEAT_1_EDX << 5U) + 11U)
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#define X86_FEATURE_MTRR ((FEAT_1_EDX << 5U) + 12U)
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#define X86_FEATURE_PGE ((FEAT_1_EDX << 5U) + 13U)
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#define X86_FEATURE_MCA ((FEAT_1_EDX << 5U) + 14U)
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#define X86_FEATURE_CMOV ((FEAT_1_EDX << 5U) + 15U)
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#define X86_FEATURE_PAT ((FEAT_1_EDX << 5U) + 16U)
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#define X86_FEATURE_PSE36 ((FEAT_1_EDX << 5U) + 17U)
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#define X86_FEATURE_PSN ((FEAT_1_EDX << 5U) + 18U)
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#define X86_FEATURE_CLF ((FEAT_1_EDX << 5U) + 19U)
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#define X86_FEATURE_DTES ((FEAT_1_EDX << 5U) + 21U)
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#define X86_FEATURE_ACPI ((FEAT_1_EDX << 5U) + 22U)
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#define X86_FEATURE_MMX ((FEAT_1_EDX << 5U) + 23U)
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#define X86_FEATURE_FXSR ((FEAT_1_EDX << 5U) + 24U)
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#define X86_FEATURE_SSE ((FEAT_1_EDX << 5U) + 25U)
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#define X86_FEATURE_SSE2 ((FEAT_1_EDX << 5U) + 26U)
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#define X86_FEATURE_SS ((FEAT_1_EDX << 5U) + 27U)
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#define X86_FEATURE_HTT ((FEAT_1_EDX << 5U) + 28U)
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#define X86_FEATURE_TM1 ((FEAT_1_EDX << 5U) + 29U)
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#define X86_FEATURE_IA64 ((FEAT_1_EDX << 5U) + 30U)
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#define X86_FEATURE_PBE ((FEAT_1_EDX << 5U) + 31U)
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/* Intel-defined CPU features, CPUID level 0x00000007 (EBX)*/
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#define X86_FEATURE_TSC_ADJ ((FEAT_7_0_EBX << 5) + 1)
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#define X86_FEATURE_SMEP ((FEAT_7_0_EBX << 5) + 7)
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#define X86_FEATURE_INVPCID ((FEAT_7_0_EBX << 5) + 10)
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#define X86_FEATURE_SMAP ((FEAT_7_0_EBX << 5) + 20)
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#define X86_FEATURE_TSC_ADJ ((FEAT_7_0_EBX << 5U) + 1U)
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#define X86_FEATURE_SMEP ((FEAT_7_0_EBX << 5U) + 7U)
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#define X86_FEATURE_INVPCID ((FEAT_7_0_EBX << 5U) + 10U)
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#define X86_FEATURE_SMAP ((FEAT_7_0_EBX << 5U) + 20U)
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/* Intel-defined CPU features, CPUID level 0x00000007 (EDX)*/
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#define X86_FEATURE_IBRS_IBPB ((FEAT_7_0_EDX << 5) + 26)
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#define X86_FEATURE_STIBP ((FEAT_7_0_EDX << 5) + 27)
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#define X86_FEATURE_IBRS_IBPB ((FEAT_7_0_EDX << 5U) + 26U)
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#define X86_FEATURE_STIBP ((FEAT_7_0_EDX << 5U) + 27U)
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/* Intel-defined CPU features, CPUID level 0x80000001 (EDX)*/
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#define X86_FEATURE_NX ((FEAT_8000_0001_EDX << 5) + 20)
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#define X86_FEATURE_PAGE1GB ((FEAT_8000_0001_EDX << 5) + 26)
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#define X86_FEATURE_LM ((FEAT_8000_0001_EDX << 5) + 29)
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#define X86_FEATURE_NX ((FEAT_8000_0001_EDX << 5U) + 20U)
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#define X86_FEATURE_PAGE1GB ((FEAT_8000_0001_EDX << 5U) + 26U)
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#define X86_FEATURE_LM ((FEAT_8000_0001_EDX << 5U) + 29U)
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#endif /*__X86_CPUFEATURES_H__*/
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@@ -89,12 +89,12 @@
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#define CPUID_TLB 2
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#define CPUID_SERIALNUM 3
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#define CPUID_EXTEND_FEATURE 7
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#define CPUID_MAX_EXTENDED_FUNCTION 0x80000000
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#define CPUID_EXTEND_FUNCTION_1 0x80000001
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#define CPUID_EXTEND_FUNCTION_2 0x80000002
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#define CPUID_EXTEND_FUNCTION_3 0x80000003
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#define CPUID_EXTEND_FUNCTION_4 0x80000004
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#define CPUID_EXTEND_ADDRESS_SIZE 0x80000008
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#define CPUID_MAX_EXTENDED_FUNCTION 0x80000000U
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#define CPUID_EXTEND_FUNCTION_1 0x80000001U
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#define CPUID_EXTEND_FUNCTION_2 0x80000002U
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#define CPUID_EXTEND_FUNCTION_3 0x80000003U
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#define CPUID_EXTEND_FUNCTION_4 0x80000004U
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#define CPUID_EXTEND_ADDRESS_SIZE 0x80000008U
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static inline void __cpuid(uint32_t *eax, uint32_t *ebx,
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@@ -112,7 +112,7 @@ static inline void cpuid(uint32_t leaf,
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uint32_t *ecx, uint32_t *edx)
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{
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*eax = leaf;
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*ecx = 0;
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*ecx = 0U;
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__cpuid(eax, ebx, ecx, edx);
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}
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@@ -48,29 +48,29 @@
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#define CPU_CONTEXT_OFFSET_R15 104U
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#define CPU_CONTEXT_OFFSET_RDI 112U
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#define CPU_CONTEXT_OFFSET_CR0 120U
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#define CPU_CONTEXT_OFFSET_RIP 152
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#define CPU_CONTEXT_OFFSET_TSC_OFFSET 184
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#define CPU_CONTEXT_OFFSET_IA32_STAR 200
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#define CPU_CONTEXT_OFFSET_IA32_LSTAR 208
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#define CPU_CONTEXT_OFFSET_IA32_FMASK 216
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#define CPU_CONTEXT_OFFSET_IA32_KERNEL_GS_BASE 224
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#define CPU_CONTEXT_OFFSET_CS 280
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#define CPU_CONTEXT_OFFSET_DS 344
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#define CPU_CONTEXT_OFFSET_ES 376
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#define CPU_CONTEXT_OFFSET_FS 408
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#define CPU_CONTEXT_OFFSET_GS 440
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#define CPU_CONTEXT_OFFSET_TR 472
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#define CPU_CONTEXT_OFFSET_GDTR 568
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#define CPU_CONTEXT_OFFSET_FXSTORE_GUEST_AREA 608
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#define CPU_CONTEXT_OFFSET_CR2 128U
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#define CPU_CONTEXT_OFFSET_CR3 136U
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#define CPU_CONTEXT_OFFSET_CR4 144U
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#define CPU_CONTEXT_OFFSET_RIP 152U
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#define CPU_CONTEXT_OFFSET_RSP 160U
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#define CPU_CONTEXT_OFFSET_RFLAGS 168U
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#define CPU_CONTEXT_OFFSET_TSC_OFFSET 184U
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#define CPU_CONTEXT_OFFSET_IA32_SPEC_CTRL 192U
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#define CPU_CONTEXT_OFFSET_IA32_STAR 200U
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#define CPU_CONTEXT_OFFSET_IA32_LSTAR 208U
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#define CPU_CONTEXT_OFFSET_IA32_FMASK 216U
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#define CPU_CONTEXT_OFFSET_IA32_KERNEL_GS_BASE 224U
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#define CPU_CONTEXT_OFFSET_CS 280U
|
||||
#define CPU_CONTEXT_OFFSET_SS 312U
|
||||
#define CPU_CONTEXT_OFFSET_DS 344U
|
||||
#define CPU_CONTEXT_OFFSET_ES 376U
|
||||
#define CPU_CONTEXT_OFFSET_FS 408U
|
||||
#define CPU_CONTEXT_OFFSET_GS 440U
|
||||
#define CPU_CONTEXT_OFFSET_TR 472U
|
||||
#define CPU_CONTEXT_OFFSET_IDTR 504U
|
||||
#define CPU_CONTEXT_OFFSET_LDTR 536U
|
||||
#define CPU_CONTEXT_OFFSET_GDTR 568U
|
||||
#define CPU_CONTEXT_OFFSET_FXSTORE_GUEST_AREA 608U
|
||||
|
||||
/*sizes of various registers within the VCPU data structure */
|
||||
#define VMX_CPU_S_FXSAVE_GUEST_AREA_SIZE GUEST_STATE_AREA_SIZE
|
||||
|
||||
Reference in New Issue
Block a user