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hv: Hypervisor access to PCI devices with 64-bit MMIO BARs
PCI devices with 64-bit MMIO BARs and requiring large MMIO space can be assigned with physical address range at the very high end of platform supported physical address space. This patch uses the board info for 64-bit MMIO window as programmed by BIOS and constructs 1G page tables for the same. As ACRN uses identity mapping from Linear to Physical address space physical addresses upto 48 bit or 256TB can be supported. Tracked-On: #4586 Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
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@ -38,6 +38,7 @@
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#include <vm.h>
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#include <ld_sym.h>
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#include <logmsg.h>
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#include <misc_cfg.h>
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static void *ppt_mmu_pml4_addr;
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static uint8_t sanitized_page[PAGE_SIZE] __aligned(PAGE_SIZE);
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@ -281,6 +282,16 @@ void init_paging(void)
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mmu_modify_or_del((uint64_t *)ppt_mmu_pml4_addr, (uint64_t)get_reserve_sworld_memory_base(),
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TRUSTY_RAM_SIZE * MAX_POST_VM_NUM, PAGE_USER, 0UL, &ppt_mem_ops, MR_MODIFY);
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#endif
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/*
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* Users of this MMIO region needs to use access memory using stac/clac
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*/
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if ((HI_MMIO_START != ~0UL) && (HI_MMIO_END != 0UL)) {
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mmu_add((uint64_t *)ppt_mmu_pml4_addr, HI_MMIO_START, HI_MMIO_START,
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(HI_MMIO_END - HI_MMIO_START), attr_uc, &ppt_mem_ops);
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}
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/* Enable paging */
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enable_paging();
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@ -13,8 +13,10 @@
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#include <security.h>
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#include <vm.h>
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static struct page ppt_pml4_pages[PML4_PAGE_NUM(CONFIG_PLATFORM_RAM_SIZE + PLATFORM_LO_MMIO_SIZE)];
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static struct page ppt_pdpt_pages[PDPT_PAGE_NUM(CONFIG_PLATFORM_RAM_SIZE + PLATFORM_LO_MMIO_SIZE)];
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#define LINEAR_ADDRESS_SPACE_48_BIT (1UL << 48U)
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static struct page ppt_pml4_pages[PML4_PAGE_NUM(LINEAR_ADDRESS_SPACE_48_BIT)];
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static struct page ppt_pdpt_pages[PDPT_PAGE_NUM(LINEAR_ADDRESS_SPACE_48_BIT)];
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static struct page ppt_pd_pages[PD_PAGE_NUM(CONFIG_PLATFORM_RAM_SIZE + PLATFORM_LO_MMIO_SIZE)];
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/* ppt: pripary page table */
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